PDF WV3EG232M64EFSU-D4 Data sheet ( Hoja de datos )

Número de pieza	WV3EG232M64EFSU-D4
Descripción	512MB - 2x32Mx64 DDR SDRAM
Fabricantes	White Electronic Designs
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White Electronic Designs WV3EG232M64EFSU-D4 ADVANCED* 512MB – 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA FEATURES Fast data transfer rate: PC-2100 and PC-2700 Clock speeds of 133 MHz and 166 MHz Two data transfers per clock cycle Supports ECC error detection and correction Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2 and 2.5 (clock) Programmable Burst Length (2, 4 or 8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect (SPD) with EEPROM Dual Rank Power supply: VCC = VCCQ = +2.5V ±0.2V (133 and 166MHz) Gold edge contacts 200 pin, small-outline, SO-DIMM package • PCB height option: 31.75 mm (1.25”) NwOwTEw: .CDoanstaulSt fahcetoeryt4foUr a.cvaoilmability of: • RoHS compliant products • Vendor source control options • Industrial temperature option DESCRIPTION The WV3EG232M64EFSU is a 2x32Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of sixteen 32Mx8 4 banks DDR SDRAMs in FBGA packages mounted on a 200 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualiﬁed or characterized and is subject to change or cancellation without notice. Clock Speed CL-tRCD-tRP OPERATING FREQUENCIES DDR333@CL=2.5 166MHz 2.5-3-3 DDR266@CL=2 133MHz 2-2-2 DDR266@CL=2.5 133MHz 2.5-3-3 April 2005 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs WV3EG232M64EFSU-D4 ADVANCED IDD SPECIFICATIONS AND CONDITIONS 0°C ≤ TA ≤ +70°C; VCC, VCCQ = +2.5V ±0.2V PARAMETER/CONDITION Operating current – One bank Active-Precharge; tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating current – One bank operation ; One bank open, BL=4, Reads — Refer to the following page for detailed test condition Percharge power-down standby current; All banks idle; power-down mode; CKE ≤ VIL(max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM Precharge Floating standby current; CS# ≥ VIH(min);All banks idle; CKE ≥ VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ,DQS and DM Precharge Quiet standby current; CS# ≥ VIH(min); All banks idle; CKE ≥ VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with keeping ≥ VIH(min) or ≤ VIL(max); VIN = VREF for DQ ,DQS and DM Active power - down standby current ; one bank active; power-down mode; CKE ≤ VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM Active standby current; CS# ≥ VIH(min); CKE ≥ VIH(min); one bank active; active - precharge; tRC = tRAS(max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; 50% of data changing at every burst; lOUT = 0mA Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst wAwutwo .rDefaretsahSchuerrent4t;UtR.Cc=omtRFC(min) - 8tCK for DDR200 at 100Mhz, 10tCK for DDR266A & DDR266B at 133Mhz; distributed refresh Self refresh current; CKE ≤ 0.2V; External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B Orerating current - Four bank operation ; Four bank interleaving with BL=4 — Refer to the following page for detailed test condition SYMBOL IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A DDR333 @CL=2.5 1160 1360 48 400 320 560 880 1720 1720 1800 48 2680 MAX DDR266 @CL=2 1000 1200 48 320 290 480 720 1480 1440 1640 48 2360 DDR266 @CL=2.5 1000 1200 48 320 290 480 720 1480 1440 1640 48 2360 Note: IDD speciﬁcation is based on Samsung components. Other DRAM Manufacturers speciﬁcation may be different. UNITS mA mA mA mA mA mA mA mA mA mA mA mA April 2005 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs WV3EG232M64EFSU-D4 ADVANCED Document Title 512MB – 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA Revision History Rev # Rev 0 History Created Release Date Status 4-05 Advanced www.DataSheet4U.com April 2005 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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