WV3EG6434S-BD4 Datasheet PDF - White Electronic Designs
| Part Number | WV3EG6434S-BD4 | |
| Description | 256MB - 32Mx64 DDR SDRAM UNBUFFERED | |
| Manufacturers | White Electronic Designs | |
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There is a preview and WV3EG6434S-BD4 download ( pdf file ) link at the bottom of this page. Total 10 Pages | ||
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White Electronic Designs
WV3EG6434S-BD4
ADVANCED*
256MB – 32Mx64 DDR SDRAM UNBUFFERED, w/PLL
FEATURES
DDR266 and DDR333
Double-data-rate architecture
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power supply: 2.5V ± 0.20V
Standard 200 pin SO-DIMM package
• Package height options:
BD4: 31.75mm (1.25")
DESCRIPTION
The WV3EG6434S is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR
SDRAM component. The module consists of eight
32Mx8 DDR SDRAMs in BGA package mounted on a
200 Pin FR4 substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Lead-Free or RoHS Products
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic Designs
WV3EG6434S-BD4
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V
DDR333@ DDR266@
CL=2.5
CL=2
Parameter
Symbol Conditions
Max Max
Operating Current
One device bank; Active - Precharge; tRC=tRC(MIN); tCK=tCK(MIN);
IDD0 DQ,DM and DQS inputs changing once per clock cycle; Address
and control inputs changing once every two cycles.
720
640
Operating Current
One device bank; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN
IDD1 );tCK=tCK(MIN); Iout = 0mA; Address and control inputs changing
once per clock cycle.
920
840
Precharge Power-Down
Standby Current
IDD2P
All device banks idle; Power- down mode; tCK=tCK(MIN);
CKE=(low)
24 24
Idle Standby Current
CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high;
IDD2F Address and other control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
240
200
Precharge Quiet
Standby Current
CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz
IDD2Q
for DDR200, 133Mhz for DDR266A & DDR266B; Address and
other control inputs stable with keeping >= VIH(min) or =
< VIL(max); VIN = VREF for DQ, DQS and DM
200
185
Active Power-Down
Standby Current
IDD3P One device bank active; Power-down mode; tCK(MIN); CKE=(low)
280
240
Active Standby Current
CS# = High; CKE = High; One device bank; Active-Precharge;
IDD3N
tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing
twice per clock cycle; Address and other control inputs changing
once per clock cycle.
440
360
Operating Current
IDD4R
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Operating Current
IDD4W
Burst = 2; Reads; Continous burst; One device bank
active;Address and control inputs changing once per clock cycle;
tCK=tCK(MIN); Iout = 0mA.
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock
cycle.
1280
1280
1120
1080
Auto Refresh Current
IDD5 tRC=tRC(MIN)
1360 1280
Self Refresh Current
IDD6 CKE ≤ 0.2V
24 24
Operating Current
Four bank interleaving Reads (BL=4) with auto precharge with
IDD7A tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change
only during Active Read or Write commands.
2240
2080
Note: IDD speicification is based on Samsung components. Other DRAM manufacturers specification may be different.
DDR266@
CL=2.5
Max
640
840
24
200
185
240
360
1120
1080
1280
24
2080
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for WV3EG6434S-BD4 electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ WV3EG6434S-BD4.PDF Datasheet ] | |
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