PDF QS532806A Data sheet ( Hoja de datos )

Número de pieza	QS532806A
Descripción	Guaranteed Low Skew 3.3V CMOS Clock Driver/buffer
Fabricantes	Integrated Device Technology
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No Preview Available ! QS532806/A GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE QS532806/A FEATURES: − JEDEC compatible LVTTL level − 10 low skew clock outputs − Monitor output − Clock inputs are 5V tolerant − Pinout and function compatible with QS5806 − 25Ω on-chip resistors for low noise − Input hysteresis for better noise margin − Guaranteed low skew: • 0.7ns output skew (same bank) • 0.9ns output skew (different bank) • 1ns part-to-part skew − Std. and A speed grades − Available in QSOP and SOIC packages DESCRIPTION The QS532806 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS532806 offers two banks of five inverting outputs. Designed in IDT's proprietary CMOS process, these devices provide low propagation delay buffering with on- chip skew of 0.7ns for same-transition, same-bank signals. The QS532806 has on-chip series termination resistors for lower noise clock signals. The series resistor versions are recommended for driving unterminated lines with capacitive loading and other noise sensitive clock distribution circuits. These clock buffer products are designed for use in high-performance workstations, embedded and personal computing sys- tems. Several devices can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. FUNCTIONAL BLOCK DIAGRAM www.DataSheet4U.com OEA IN A IN B OEB 5 OA5 - OA1 MON 5 OB5 - OB1 INDUSTRIAL TEMPERATURE RANGE c 1999 Integrated Device Technology, Inc. 1 SEPTEMBER 2000 DSC-5783/- 1 page QS532806/A GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER TEST CIRCUITS AND WAVEFORMS Pulse Generator VIN 50Ω VCC DUT VOUT 50pF INDUSTRIAL TEMPERATURE RANGE Parameter Tested tPLZ, tPZL All Others Switch Position Closed Open 500Ω 6.0 V 500Ω Pulse generator for all pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns INPUT OUPUT tPLH tPHL tR PROPAGATION DELAY tF 3V 1.5V 0V VOH 2.0V 1.5V 0.8V VOL IN PU T OUPUT 1 tPLH1 tPHL1 www.DataSheet4U.com OUPUT 2 tS K( 0 1 ) tS K( 0 1 ) tPLH2 tPHL2 tSK(01) = tPLH2 - tPLH1 or tPHL2 - tPHL1 OUTPUT SKEW (SAME BANK) — tSK(O1) 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL INPUT OUPUT tPLH tPHL tSK(p) = tPHL - tPLH PULSE SKEW — tSK(P) 3V 1.5V 0V VOH 1.5V VOL INPUT OUPUT A tP L HA tPHLA OUPUT B tS K( 0 2 ) tSK(02) tPLHB tPHLB tSK(02) = tPLHB - tPLHA or tPHLB - tPHLA OUPUT SKEW (DIFFERENT BANKS) — tSK(O2) 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL CONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIG H ENABLE tPZL SWITCH CLOSED tPZH SWITCH OPEN 1.5V 1.5V DISABLE tP L Z tPHZ 3V 1.5V 0V 3V 0.3V VOL 0.3V VOH 0V ENABLE AND DISABLE TIMES INPUT PART 1 OUTPUT PART 2 OUTPUT 5 tPLH1 tPHL1 tSK(t) tSK(t) tPLH2 tPHL2 tSK(t) = tPLH2 - tPLH1 or tPHL2 - tPHL1 PART-TO-PART SKEW — tSK(T) 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL 5 Page

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Número de pieza	Descripción	Fabricantes
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