FIN210AC Datasheet PDF - Fairchild Semiconductor
| Part Number | FIN210AC | |
| Description | 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz | |
| Manufacturers | Fairchild Semiconductor | |
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There is a preview and FIN210AC download ( pdf file ) link at the bottom of this page. Total 17 Pages | ||
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June 2009
FIN210AC
10-Bit Serializer / Deserializer Supporting Cameras and
Small Displays up to 48MHz
Features
Data & Control Bits
Frequency
Capability
Interface
µController Usage
Selectable Edge Rates
Standby Current
Core Voltage (VDDA/S)
I/O Voltage (VDDP)
ESD (I/O to GND)
Package
Ordering Information
10-bit
48MHz
Camera or LCD
Microcontroller, RGB, YUV
m68 & i86
Yes
<10µA
2.8 to 3.6V
1.65 to 3.6V
15kV
32-Terminal MLP (Preliminary)
42-Ball USS-BGA
FIN210ACMLX (Preliminary)
FIN210ACGFX
Description
The FIN210AC µSerDes™ is a low-power serializer /
deserializer optimized for use in cell phone displays and
camera paths. The device reduces a 10-bit data path to four
wires. For camera applications, an additional master clock
can be passed in the opposite direction of data flow. The
device utilizes Fairchild’s proprietary ultra-low power, low-
EMI technology.
Applications
Slider, Folder, & Clamshell Mobile Handsets
Printers
Security Cameras
Typical Application
www.DataSheet4U.com
Baseband
Related Resources
For samples and questions, please contact:
FIN210AC
Internal
Termination
Built-in voltage
translation
FIN210AC
Camera
Module
+ 2+
-
-
2
++
--
CTL™
Isolates interface
for signal integrity
Camera
Module
Up to 48MHz
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
Figure 1. Mobile Phone Example
www.fairchildsemi.com
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Table 3. Deserializer S0 & S1 Control Pins (Note: All edge rates are typical values)
Slow Edge Rates
LVCMOS Output Edge Rates
~7 - 8ns (CL = 8pF)
S0
0
Medium Edge Rates
~4 - 5ns (CL = 8pF)
1
Fast Edge Rates
~2 - 3ns (CL = 8pF)
1
Power Down
0
S1
1
1
0
0
Pulse Width Calculations
CKP Pulse Width Low Time=(PLL Multiplier • Pwidth Multiplier) / (CKREF•12)
Example: CKREF=26MHz; PLL Multiplier=1; Pwidth Multiplier=6
CKP Pulse width=(1 • 6) / (26MHz • 12)=19.2ns
CKREF = Strobe 50% Duty Cycle
If CKREF = Strobe the below control states will provide a ~ 50% duty cycle pulse width output on CKP
Table 4. CKREF = Strobe 50% Duty Cycle
PLL0
1
Serializer
PLL1
0
PWS0
0
Deserializer
PWS1
0
(1)
(2)
Power-Down States
When both S1 and S0 signals are 0, regardless of the state of the DIRI signal, the FIN210AC resets and powers down. The
power-down mode shuts down all internal analog circuitry, disables the serial input and output of the device, and resets all
www.DaintateSrhneaelt4dUig.ictoaml logic. Table 5 indicates the state of the input states and output buffers in Power-Down mode.
Table 5. Power-Down
Signal Pins
DP[1:10]
CKP
STROBE
CKREF
/DIRO
DIRI=1 (Serializer)
Inputs Disabled
HIGH
Input Disabled
Input Disabled
0
DIRI=0 (Deserializer)
/ENZ = 0
Outputs High-Z
High-Z
Input Disabled
Input Disabled
1
DIRI=0 (Deserializer)
/ENZ = 1
Outputs Low
High
Input Disabled
Input Disabled
1
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
5
www.fairchildsemi.com
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for FIN210AC electronic component. |
| Information | Total 17 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ FIN210AC.PDF Datasheet ] | |
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| Part Number | Description | MFRS |
| FIN210AC | The function is 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz. Fairchild Semiconductor | |
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