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PDF FX-702 Data sheet ( Hoja de datos )
| Número de pieza | FX-702 | |
| Descripción | Low Jitter VCSO Frequency Translator | |
| Fabricantes | Vectron International | |
| Logotipo |  |
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FX-702
Low Jitter VCSO Frequency Translator
Previous Part Number FX-730
FX-702
Description
The FX-702 is a low jitter precision frequency translator used to translate input frequencies such as 19.44, 38.88, 77.76 MHz, etc. to
a binary multiple frequency as high as 850 MHz. The FX-702’s superior jitter performance is achieved through the PLL’s integrated
VCSO. The FX-702 is housed in a hermetically sealed leadless surface mount package offered on tape and reel.
Features
Applications
• 5 x 7.5 x 2.5 mm Package
• Frequency Translation up to 850 MHz
• VCSO based PLL for Ultra-Low Jitter
• CMOS / LVDS / LVPECL Inputs compatible
• Differential LVPECL or LVDS Output
• CMOS Lock Detect
• External Divider for Input Frequencies < 19 MHz
• 0°/70°C or -40°/+85°C Temperature Range
www.D• aFtuaSllhyeCeot4mU.pcaomtible for Lead Free Assembly
• SONET/SDH
• 10GbE./10.3GbE
• Frequency Translation
• Clock Smoothing, Clock Switching
• FEC Scaling
Block Diagram
1 of 7
VCC
(10)
FIN
(12) ÷1, ÷4
CFIN
(11)
MODE
(4)
LD
(2)
Phase
Detector
& LD
LFN
(6)
Charge
Pump
CFLN
(7)
VCSO
Switch
External
Divider
÷1, ÷4, ÷8,
÷16, ÷32
÷1, ÷2, ÷4
BRCLK CBRCLK
(1) (4)
Figure 1. Functional block diagram
FOUT
(8)
CFOUT
(9)
GND
(3, 5, 13)
Vectron International • 267 Lowell Road1, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 03Apr2009
1 page  
FX702 YWW
CCC-CCCC
▲ XX-XX
Figure 5. Outline Diagram
Table 7. Pin Functions
Pad #
Symbol
1 BRCLK
2 LD1
3 GND
4 MODE2
5 GND
I/O Level
Function
I NC or LVPE- NC or
CL, LVDS For External divider application = PD Feedback Frequency
O CMOS Lock Detect
Logic 0 = FX Locked
Logic 1 - No Input
Output transitioning = Out of Lock
GND Supply Case and electrical ground
I CMOS FX Operating Mode
Logic 0 = Standard PLL (Normal Setting)
Logic 1 = FIN coupled to FOUT
GND Supply Case and electrical ground
6 LFN
Analog Loop Filter Node
7 CLFN
www.DataS8heet4U.comFOUT
9 CFOUT
10 VCC
Analog Complementary Loop Filter Node
O LVPECL or Frequency Output
LVDS
O LVPECL or Complementary Frequency Output
LVDS
I Supply Power Supply Voltage (+3.3V ±5%)
11 CFIN
12 FIN
I LVPECL Complemetary Input Frequency
For CMOS inouts, AC-couple unused inputto ground or negative supply
I CMOS or Input Frequency
LVPECL
13 GND GND Supply Case and electrical ground
14 CBRCLK
I NC or LVPE- NC or
CL, LVDS For External divider applications = Comp. PD Feedback Frequency
1. It is recommended that a buffer driver is used for best noise isolation.
2. Do not leave the MODE pin floating, it should be set to logic 0 or ground for normal operation.
3. BRCLK and CBRCLK should be left floating if not used.
4. FIN, CFIN, BRCLK, and CBRCLK have internal pull-up/pull-down resistors and it is recommended to AC couple these inputs.
5 of 7
Vectron International • 267 Lowell Road5, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 03Apr2009
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet FX-702.PDF ] | |
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