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PDF AT52SC1284J Data sheet ( Hoja de datos )
| Número de pieza | AT52SC1284J | |
| Descripción | (AT52SC1283J / AT52SC1284J) 128-Mbit Flash + 32-Mbit/64-Mbit | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Module Features
• 128-Mbit Burst/Page Flash + 32-Mbit/64-Mbit PSRAM
• Single 88-ball (8 mm x 10 mm x 1.2 mm) CBGA Package
• 1.7V to 1.95V VCC
• 1.8V to 1.95V for VCCQ and PVCC
128-Mbit Flash Features
• 8M x 16 Organization
• High Performance
– Random Access Time – 70 ns, 85 ns
– Page Mode Read Time – 20 ns
– Synchronous Burst Frequency – 66 MHz
– Configurable Burst Operation
• Sector Erase Architecture
– Sixteen 4K Word Sectors with Individual Write Lockout
– Two Hundred Fifty-four 32K Word Main Sectors with Individual Write Lockout
• Typical Sector Erase Time: 32K Word Sectors – 800 ms; 4K Word Sectors – 200 ms
• Thirty-two Plane Organization, Permitting Concurrent Read in Any of the Thirty-one
Planes not Being Programmed/Erased
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
– 30 mA Active
– 20 µA Standby
• VPP Pin for Write Protection and Accelerated Program Operations
• RESET Input for Device Initialization
• Two Protection Registers (128 Bits + 2,048 Bits)
• Common Flash Interface (CFI)
ww•wT.DoaptaaSnhdeeBt4oUt.tcoomm Boot Sectors
• 1.7V to 1.95V Operating Voltage
Asynchronous/Page PSRAM Features
• 32-Mbit (2M Word x 16)/64-Mbit (4M Word x 16)
• 70 ns Random Access Time
• 30 ns Page Read Cycle Time
• 1.8V to 1.95V Operating Voltage
• <10 µA Deep Standby Power
128-Mbit Flash
+ 32-Mbit/64-Mbit
PSRAM
Stack Memory
AT52SC1283J
AT52SC1284J
Preliminary
Stack Module Memory Contents
Device
AT52SC1283J
AT52SC1284J
Memory Combination
128M Flash + 32M PSRAM
128M Flash + 64M PSRAM
3530B–STKD–2/4/05
1 page  
AT52SC1283J/1284J [Preliminary]
the device. The access time is measured from stable address, falling edge of AVD or falling
edge of CE, whichever occurs last. During the AVD pulsed read, the CLK signal may be static
high or static low. For standard asynchronous reads, the AVD and CLK signal should be tied to
GND. The asynchronous read diagrams are shown on page 30.
6.4 Page Read
The page read operation of the device is controlled by CE, OE, and AVD inputs. The CLK input
is ignored during a page read operation and should be tied to GND. The page size is four words.
During a page read, the AVD signal can transition low and then transition high, transition low and
remain low, or can be tied to GND. If a high to low transition on the AVD signal occurs, as shown
in Page Read Cycle Waveform 1, the page address is latched by the low-to-high transition of the
AVD signal. However, if the AVD signal remains low after the high-to-low transition or if the AVD
signal is tied to GND, as shown in Page Read Cycle Waveform 2, then the page address (A22 -
A2) cannot change during a page read operation. The first word access of the page read is the
same as the asynchronous read. The first word is read at an asynchronous speed of 70 ns.
Once the first word is read, toggling A0 and A1 will result in subsequent reads within the page
being output at a speed of 20 ns. If the AVD and the CLK pins are both tied to GND, the device
will behave like a standard asynchronous Flash memory. The page read diagrams are shown on
page 23.
6.5 Synchronous Reads
Synchronous reads are used to achieve a faster data rate that is possible in the asynchro-
nous/page read mode. The device can be configured for continuous or fixed-length burst
access. The burst read operation of the device is controlled by CE, OE, CLK and AVD inputs.
The initial read location is determined as for the AVD pulsed asynchronous read operation; it can
be any memory location in the device. In the burst access, the address is latched on the rising
edge of the first clock pulse when AVD is low or the rising edge of the AVD signal, whichever
occurs first. The CLK input signal controls the flow of data from the device for a burst operation.
After the clock latency cycles, the data at the next burst address location is read for each follow-
ing clock cycle.
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Figure 6-1. Word Boundary
Word D0 - D3
Word D4 - D7
Word D8 - D11 Word D12 - D15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
16-word Boundary
6.6 Continuous Burst Read
During a continuous burst read, any number of addresses can be read from the memory. When
operating in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device
may incur an output delay when the burst sequence crosses the first 16-word boundary in the
memory (see Figure 6-1). If the starting address is D0 - D12, there is no delay. If the starting
address is D13 - D15, an output delay equal to the initial clock latency is incurred. The delay
3530B–STKD–2/4/05
5
5 Page 
AT52SC1283J/1284J [Preliminary]
Table 6-3. Status Register Bit Definition
WSMS
ESS
ES
PRS
VPPS
PSS
SLS
PLS
76543210
Notes
SR7 WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
SR4 = PROGRAM STATUS (PRS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1”, WSM has attempted but failed to
program a word
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous indication of VPP
level. The WSM interrogates VPP level only after the Program or
Erase command sequences have been entered and informs the
system if VPP has not been switched on. The VPP is also checked
before the operation is verified by the WSM.
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
SR1 = SECTOR LOCK STATUS
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
SR0 = Plane Status (PLS)
Indicates program or erase status of the addressed plane.
wwNwo.tDea: taSh1e.etA4UC.coommmand Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
Table 6-4.
WSMS
(SR7)
0
0
1
Status Register Device WSMS and Write Status Definition
PLS
(SR0)
Description
0 The addressed plane is performing a program/erase operation.
1 A plane other than the one currently addressed is performing a program/erase operation.
x
No program/erase operation is in progress in any plane. Erase and Program suspend bits (SR6, SR2)
indicate whether other planes are suspended.
3530B–STKD–2/4/05
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