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PDF T80C5112 Data sheet ( Hoja de datos )
| Número de pieza | T80C5112 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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8-bit Microcontroller with A/D converter
T80C5112
1. Description
The T80C5112 is a high performance ROM/OTP version
of the 80C51 8-bit microcontroller.
The T80C5112 retains all the features of the standard
80C51 with 8 Kbytes ROM/OTP program memory, 256
bytes of internal RAM, a 8-source , 4-level interrupt
system, an on-chip oscillator and two timer/counters.
The T80C5112 is dedicated for analog interfacing
applications. For this, it has an 10-bit, 8 channels A/D
converter and a five channels Programmable Counter
Array.
In addition, the T80C5112 has a Hardware Watchdog
Timer with its own low power oscillator, a versatile
serial channel that facilitates multiprocessor
communication (EUART) with an independent baud rate
generator, a SPI serial bus controller and a X2 speed
improvement mechanism. The X2 feature allows to keep
the same CPU power at a divided by two oscillator
frequency.
The fully static design of the T80C5112 allows to reduce
system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The T80C5112 has 3 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the peripherals are still operating. In the quiet mode, the
A/D converter only is operating. In the power-down
mode the RAM is saved and all other functions are
inoperative. Two oscillators source, crystal and RC,
provide a versatile power management.
The T80C5112 is proposed in 48/52 pin count packages
with Port 0 and Port 2 (address / data busses).
2. Features
· 80C51 Compatible
· Crystal or ceramic oscillator with hardware set
· Five I/O ports
up (32 KHz or 33/40 MHz)
· Two 16-bit timer/counters
· Internal RC oscillator (12 MHz)
· 256 bytes RAM
· Programmable prescaler
· 8Kbytes ROM/OTP program memory with 64 bytes
www.DataSheete4nUc.cryopmtion array and 3 security levels.
· Active oscillator during reset defined by hardware
set up
· High-Speed Architecture
· Timer 0 subclock mode for Real Time Clock.
· Programmable counter array with High speed output,
· 33MHz @ 5V (66 MHz equivalent)
Compare / Capture, Pulse Width Modulation and
· 20MHz @ 3V (40 MHz equivalent)
Watchdog timer capabilities
· X2 Speed Improvement capability (6 clocks/ · Interrupt Structure with:
·
·
machine cycle)
10-bit, 8 channels A/D converter
Hardware Watchdog Timer with integrated low
power oscillator (20m A) and Reset-Out
·
· 8 Interrupt sources,
· 4 interrupt priority levels
Power Control modes:
· Programmable I/O mode: standard C51, input only,
· Idle mode
push-pull, open drain.
· Power-down mode
· Asynchronous port reset, Power On Reset
· Power-off Flag, Power fail detect, Power on Reset
· Full duplex Enhanced UART with baud rate generator · Power supply: 2.7 to 5.5V
· SPI, master/slave mode
· Temperature ranges: Commercial (0 to 70C) and
Industrial (-40 to 85 C), optionnal extented
· Dual system clock
· Package:LQFP48 (body 7*7*1.4mm), PLCC52
Rev. B - November 10, 2000
Preliminary
1
1 page  
T80C5112
PIN
NUMBER
TYPE
MNEMONIC LQFP PLCC
NAME AND FUNCTION
VSS
VCC
AVSS
AVCC
VREF
VPP
P1.0-P1.7
P3.0-P3.7
www.DataSheet4U.com
P4.0-P4.7
48 52
XX
I Ground: 0V reference.
XX
I
Power Supply: This is the power supply voltage for normal, idle and power-
down operation.
X I Analog Ground: 0V reference.
I
Analog Power Supply: This is the power supply voltage for normal and idle
operation of the A/D
XX
I VREF : A/D converter positive reference input.
XX
Vpp : Programming Supply Voltage:
I This pin also receives the 12V programming pulse which will start the EPROM
programming and the manufacturer test modes.
X
X
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs.
Alternate functions for Port 1 include:
I/O WR (P1.0): External data memory write strobe
I/O RD (P1.1): External data memory readstrobe
I/O ECI (P1.2): External Clock for the PCA
I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0
I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1
I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2
I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3
I/O CEX4 (P1.7): Capture/Compare External I/O for PCA module 4
X
X
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs.
P3.4 and P3.5 are valid I/O pins only when the T80C5112 is using the internal
RC oscillator, OSCB.
P3.6 is an input only pin
Port 3 also serves the special features of the 80C51 family, as listed below.
I/O RXD (P3.0): Serial input port
I/O TXD (P3.1): Serial output port
I/O INT0 (P3.2): External interrupt 0
I/O T0 (P3.3): Timer 0 external input
I/O
XTAL1 (P3.4): Input to the inverting oscillator amplifier and input to the internal
clock generator circuits, selected by hardware set upa
I/O
XTAL2 (P3.5): Output from the inverting oscillator amplifier, selected by
hardware set up
Port 4: Port 4 is an 8-bit bidirectional I/O port. Each bit can be set as pure
X
X
I/O
CMOS input or as push-pull output.
Port 4 is also the input port of the Analog to digital converter and used for
oscillator and reset.
I/O AIN0 (P4.0): A/D converter input 0
I/O
AIN1 (P4.1): A/D converter input 1
T1: Timer 1 external input
I/O
AIN2 (P4.2): A/D converter input 2
SS: Slave select input of the SPI controller
Rev. B - November 10, 2000
Preliminary
5
5 Page 
T80C5112
· A software instruction which set X2 bit desactivates the precaler/divider, so the internal clock is either Xtal_Osc
or RC_Osc depending on SEL_OSC bit.
6.5. Timer 0 : Clock Inputs
CkIdle
T0 pin
Sub Clock
:6
0
1
SCLKT0
OSCCON
0
1
C/T
TMOD
Control
Timer 0
Gate
INT0
TR0
Figure 2. Timer 0 : Clock Inputs
The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. This allow to perform a Real
Time Clock function.
SCLKT0 = 0 : Timer 0 uses the standard T0 pin as clock input ( Standard mode )
SCLKT0 = 1 : Timer 0 uses the special Sub Clock as clock input.
When the subclock input is selected for Timer 0 and the crystal oscillator is selected for CPU and peripherals, the
CKRL prescaler must be set to FF (division factor 2) in order to assure a proper count on Timer 0.
With a 32 kHz crystal, the timer interrupt can be set from 1/256 to 256 seconds to perform a Real Time Clock
www.DataSh(ReeTt4CU).cfoumnction. The power consumption will be very low as the CPU is in idle mode at 32 KHz most of the time.
When more CPU power is needed, the internal RC oscillator is activated and used by the CPU and the others
peripherals.
6.6. Registers
6.6.1. Configuration byte
The configuration byte is a special register. Its content is defined by the diffusion mask in the ROM version or
is rerad or written by the OTP programmer in the OTP version. This register can also be accessed as a read only
register.
CONF - Configuration byte (EFh)
76543210
LB1
LB2
LB3
RST_OSC
XT_SP
RST_EXT OSCC_OFF
Bit
Number
7:5
Bit Description
Mnemonic
- Program memory lock bits
See chapter program memory for the deÞnition of these bits..
Rev. B - November 10, 2000
Preliminary
11
11 Page | ||
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