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PDF BLD6G22L-50 Data sheet ( Hoja de datos )
| Número de pieza | BLD6G22L-50 | |
| Descripción | W-CDMA 2110 MHz To 2170 MHz Fully Integrated Doherty Transistor | |
| Fabricantes | NXP Semiconductors | |
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BLD6G22L-50; BLD6G22LS-50
W-CDMA 2110 MHz to 2170 MHz fully integrated Doherty
transistor
Rev. 01 — 15 December 2009
Objective data sheet
1. Product profile
1.1 General description
The BLD6G22L-50 and BLD22LS-50 incorporate a fully integrated Doherty solution using
NXP’s state of the art GEN6 LDMOS technology. This device is perfectly suited for CDMA
base station applications at frequencies from 2110 MHz to 2170 MHz. The main and peak
device, input splitter and output combiner are integrated in a single package. This
package consists of one gate and drain lead and two extra leads of which one is used for
biasing the peak amplifier and the other is not connected. It only requires the proper
input/output match and bias setting as with a normal class-AB transistor.
Table 1. Typical performance
RF performance at Th = 25 °C.
Mode of operation
f
(MHz)
W-CDMA [1][2]
2110 to 2170
VDS PL(AV)
(V) (W)
28 8
Gp
(dB)
13.3
ηD
(%)
38
ACPR
(dBc)
−30
PL(3dB)
(W)
52
[1] Test signal: 2-carrier W-CDMA; test model 1; 64 DPCH; PAR = 8.3 dB at 0.01 % probability on CCDF;
carrier spacing 5 MHz.
[2] IDq = 170 mA (main); VGS(amp)peak = 0 V.
CAUTION
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This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features
Typical W-CDMA performance at frequencies from 2110 MHz to 2170 MHz:
Average output power = 8 W
Power gain = 13.3 dB
Efficiency = 38 %
Fully optimized integrated Doherty concept:
integrated asymmetrical power splitter at input
integrated power combiner
peak biasing down to 0 V
low junction temperature
high efficiency
1 page  
NXP Semiconductors
BLD6G22L-50; BLD6G22LS-50
W-CDMA 2110 MHz to 2170 MHz fully integrated Doherty transistor
8.2 Impedance information
Table 8. Typical impedance
Measured load-pull data; typical values unless otherwise specified.
f
MHz
ZS
Ω
ZL
Ω
2050
9.4 − 12.3j
5.5 − 7.6j
2110
11.4 − 11.2j
6.7 − 8.2j
2140
12.3 − 10.5j
7.0 − 7.5j
2170
12.2 − 9.3j
7.2 − 6.8j
2230
11.8 − 7.3j
5.4 − 5.5j
gate
ZS
drain
ZL
001aaf059
Fig 2. Definition of transistor impedance
www.DataSheet4U.com
BLD6G22L-50_BLD6G22LS-50_1
Objective data sheet
Rev. 01 — 15 December 2009
© NXP B.V. 2009. All rights reserved.
5 of 15
5 Page 
NXP Semiconductors
BLD6G22L-50; BLD6G22LS-50
W-CDMA 2110 MHz to 2170 MHz fully integrated Doherty transistor
10. Package outline
Flanged ceramic package; 2 mounting holes; 4 leads
SOT1130A
D
A
L
D1
U1
q
1
F
B
Cc
H U2
p E1
E
www.DataSheet4U.comA
4
b
3
w1 A B
25
b1 w2 C
Q
Dimensions
0 5 10 mm
scale
Unit(1) A b b1 c D D1 E E1 F H L p Q q U1 U2 w1 w2
max 4.65 1.14 5.26 0.18 9.65
mm nom
min 3.76 0.89 5.00 0.10 9.40
max 0.183 0.045 0.207 0.007 0.38
inches nom
min 0.148 0.035 0.197 0.004 0.37
9.65
9.40
0.38
0.37
9.65
9.40
0.38
0.37
9.65 1.14 17.12 3.00 3.30 1.70
20.45
15.24
9.40 0.89 16.10 2.69 2.92 1.45
20.19
0.38 0.045 0.674 0.118 0.130 0.067
0.805
0.6
0.37 0.035 0.634 0.106 0.115 0.057
0.795
9.91
9.65
0.39
0.38
0.25
0.01
0.51
0.02
Note
1. Millimeter dimensions are derived from the original inch dimensions.
sot1130a_po
Outline
version
References
IEC
JEDEC
JEITA
European
projection
Issue date
SOT1130A
09-07-23
09-10-12
Fig 14. Package outline SOT1130A
BLD6G22L-50_BLD6G22LS-50_1
Objective data sheet
Rev. 01 — 15 December 2009
© NXP B.V. 2009. All rights reserved.
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