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PDF AT88SA100S Data sheet ( Hoja de datos )
| Número de pieza | AT88SA100S | |
| Descripción | Battery Authentication Chip | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Secure battery authentication
• Superior SHA-256 Hash Algorithm
• Best in class 256 bit key length
• Guaranteed Unique 48 bit Serial Number
• High speed single wire interface
• Supply Voltage: 2.5 – 5.5V
• <100nA Sleep Current
• 4KV ESD protection
• Green compliant (exceeds RoHS) 3 pin SOT-23 package
Applications
• Cell Phones
• PDA and Smart Phones
• Portable Media Players
• Digital Cameras & Camcorders
• Cordless Tools
• Handheld Devices
1. Introduction
The AT88SA100S is a small authentication chip that can be used to
validate battery packs and other replaceable items that contain a
power source. It uses the industry leading SHA-256 hash algorithm
to provide the ultimate level of security.
An industry leading key length of 256 bits prevents exhaustive
attacks while multiple physical security features prevent
unauthorized disclosure of the secret key stored within the chip.
This key is automatically erased when power is removed from the
www.DataSheet4dUev.cicoem.
It is shipped with a guaranteed unique 48 bit serial number that is
used in combination with an input challenge and the stored secret
key to generate a response that is unique for every individual
device.
The chip also includes 80 one-time fuses that can be used to
configure the system and/or retain permanent status. The values in
these fuses can also be locked to prevent modification.
CryptoAuthentication™
AT88SA100S
Battery Authentication
Chip
Preliminary
8558B–SMEM–09/09
1 page  
2.2. AC Parameters
Figure 1. AC Parameters
WAKE
tWLO
AT88SA100S [ Preliminary]
data comm
tWHI
LOGIC Ø
LOGIC 1
NOISE
SUPPRESION
www.DataSheet4U.com
tSTART
tZHI
tZLO
tBIT
tSTART
tLIGNORE
tHIGNORE
8558B–SMEM–09/09
5
5 Page 
AT88SA100S [ Preliminary]
3.4.1.
IO Timeout
After a leading transition for any data token has been received, the device will expect another token to be transmitted
within a tTIMEOUT interval. If the leading edge of the next token is not received within this period of time, the device
assumes that the synchronization with the host is lost and transitions to a sleep state.
After the device receives the last bit of a command block, this timeout circuitry is disabled. If the command is properly
formatted, then the timeout counter is re-enabled with the first transmit token that occurs after tPARSE + tEXEC . If there
is an error in the command, then it is re-enabled with the first transmit token that occurs after tPARSE .
In order to limit the active current if the device is inadvertently awakened, the IO timeout is also enabled when the
device wakes up. If the first token does not come within the tTIMEOUT interval, then the device will go back to sleep
without performing any operations.
3.4.2. Synchronization Procedures
When the system and the device fall out of synchronization, the system will ultimately end up sending a transmit flag
which will not generate a response from the device. The system should implement its own timeout which waits for
tTIMEOUT during which time the device should go to sleep automatically. At this point, the system should send a Wake
token and after tWLO + tWHI, a Transmit token. The 0x11 status indicates that the resynchronization was successful.
It may be possible that the system does not get the 0x11 code from the device for one of the following reasons:
1. The system did not wait a full tTIMEOUT delay with the IO signal idle in which case the device may have interpreted
the Wake token and Transmit flag as a data bits. Recommended resolution is to wait twice the tTIMEOUT delay and
re-issue the Wake token.
2. The device went into the sleep mode for some reason while the system was transmitting data. In this case, the
device will interpret the next data bit as a wake token, but ignore some of the subsequently transmitted bits during
its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be interpreted as a legal flag,
though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of a
correct CRC. Recommended resolution is to wait the tTIMEOUT delay and re-issue the Wake token.
3. There is some internal error condition within the device which will be automatically reset after a tWATCHDOG interval,
see below. There is no way to externally reset the device – the system should leave the IO pin idle for this interval
and issue the Wake token.
3.5. Watchdog Failsafe
After the Wake token has been received by the device, a watchdog counter is started within the chip. After tWATCHDOG,
www.DataSheet4thUe.ccohmip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether
some IO transmission is in progress. There is no way to reset the counter other than to put the chip to sleep and wake
it up again.
This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state
machines of the device including any IO synchronization issue, power consumption will fall to the low sleep level
automatically.
3.6.
Byte and Bit Ordering
The device is a little-endian chip:
• All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the order
received.
• Data is transferred to/from the device least significant bit first on the bus.
• In this document, the most significant bit appears towards the left hand side of the page.
8558B–SMEM–09/09
11
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