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Cypress Semiconductor - (CG6457AM / CG6462AM) FAN Controller

Numéro de référence CG6457AM
Description (CG6457AM / CG6462AM) FAN Controller
Fabricant Cypress Semiconductor 
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CG6457AM fiche technique
PSoC™ Mixed-Signal Array
FAN Controller
CG6457AM and CG6462AM
Preliminary Data Sheet
Features
Excellent for Fan Control Applications
Powerful Harvard Architecture Processor
M8C Processor Speeds to 12 MHz
Low Power at High Speed
4.75V to 5.25V Operating Voltage
Extended Temperature Range:
-40°C to +125°C
Advanced Peripherals (PSoC Blocks)
4 Analog Type “E” PSoC Blocks Provide:
- 2 Comparators with DAC Refs
- Single or Dual 8-Bit 8:1 ADC
4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART, SPIMaster or Slave
- Connectable to All GPIO Pins
Complex Peripherals by Combining Blocks
Flexible On-Chip Memory
4K Flash Program Storage
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
Flexible Protection Modes
Complete Development Tools
Free Development Software
(PSoC™ Designer)
Full-Featured, In-Circuit Emulator and
Programmer
Full Speed Emulation
Complex Breakpoint Structure
128 Bytes Trace Memory
Precision, Programmable Clocking
Internal ±3.5% 24 MHz Oscillator
Internal Oscillator for Watchdog and Sleep
Programmable Pin Configurations
25 mA Drive on All GPIO
Pull Up, Pull Down, High Z, Strong, or Open
Drain Drive Modes on All GPIO
Up to 8 Analog Inputs on GPIO
Configurable Interrupt on All GPIO
Additional System Resources
I2C™ Master, Slave and Multi-Master to
400 kHz
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
PSoC
CORE
SystemBus
Port 1 Port 0
Global Digital Interconnect
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Global Analog Interconnect
SRAM
Interrupt
Controller
SROM
Flash
CPU Cor e
(M8C)
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
Digital
PSoC Block
Array
ANALOG SYSTEM
Analog
PSoC Block
Array
Analog
Ref .
Digital
Clocks
POR and LVD
I2 C
System Resets
SYSTEM RESOURCES
Internal
Voltage
Ref .
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable component. A
PSoC device includes configurable blocks of analog and digital
logic, as well as programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application. Addi-
tionally, a fast CPU, Flash program memory, SRAM data mem-
ory, and configurable IO are included in a range of convenient
pinouts.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow all the device resources to be combined into a
complete custom system. Each PSoC device includes four digi-
tal blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 general purpose IO (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO (inter-
nal main oscillator) and ILO (internal low speed oscillator). The
May 24, 2005
© Cypress Semiconductor Corp. 2005 — Document No. 001-00353 Rev. **
1

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