PDF WCMA2016U4X Data sheet ( Hoja de datos )

Número de pieza	WCMA2016U4X
Descripción	128K x 16 STATIC
Fabricantes	Weida Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de WCMA2016U4X (archivo pdf) en la parte inferior de esta página. Total 11 Páginas
No Preview Available ! WCMA2016U4X WCMA2016U4X Features • Low Voltage range: — 2.7V-3.3V • Ultra-low active power — Typical active current: 1.5 mA @ f = 1MHz — Typical active current: 7 mA @ f = fmax • Low standby power • Easy memory expansion with CE and OE features • Automatic power-down when deselected • CMOS for optimum speed/power Functional Description The WCMA2016U4X is a high-performance CMOS static RAMs organized as 128K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active cur- rent. This device is ideal for portable applications such as cel- lular telephones. The devices also have an automatic pow- er-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by 128K x 16 Static RAM more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High En- able and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The WCMA2016U4X is available in a 48-ball FBGA package. Logic Block Diagram www.DataSheet4U.com A1010 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DATA IN DRIVERS 128K x 16 RAM Array 2048 x 1024 I/O0 – I/O7 I/O8 – I/O15 COLUMN DECODER Power -Down Circuit CE BHE BLE BHE WE CE OE BLE 1 page WCMA2016U4X Switching Characteristics Over the Operating Range[8] 70 ns Parameter Description Min Max Unit READ CYCLE tRC Read Cycle Time 70 ns tAA Address to Data Valid 70 ns tOHA Data Hold from Address Change 10 ns tACE CE LOW to Data Valid 70 ns tDOE tLZOE tHZOE tLZCE tHZCE OE LOW to Data Valid OE LOW to Low Z[9] OE HIGH to High Z[9, 11] CE LOW to Low Z[9] CE HIGH to High Z[9, 11] 35 ns 5 ns 25 ns 10 ns 25 ns tPU CE LOW to Power-Up 0 ns tPD CE HIGH to Power-Down 70 ns tDBE tLZBE[10] tHZBE WRITE CYCLE[12] BHE / BLE LOW to Data Valid BHE / BLE LOW to Low Z[9] BHE / BLE HIGH to High Z[9, 11] 5 70 ns ns 25 ns tWC Write Cycle Time 70 ns tSCE CE LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 50 ns tBW www.DtSaDtaSheet4U.com BHE / BLE Pulse Width Data Set-Up to Write End 60 30 ns ns tHD tHZWE tLZWE Data Hold from Write End WE LOW to High Z[9, 11] WE HIGH to Low Z[9] 0 ns 25 ns 10 ns Notes: 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. If both byte enables are toggled together this value is 10ns 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.. 5 5 Page WCMA2016U4X Document Title: WCMA2016U4X, 128K x 16 STATIC RAM Document Number: 38-05212 REV. ECN NO. Issue Date Orig. of Change ** 112910 1/17/02 MGN Description of Change New Datasheet www.DataSheet4U.com 11 11 Page

Páginas	Total 11 Páginas
PDF Descargar	[ Datasheet WCMA2016U4X.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
WCMA2016U4B	128K x 16 Static RAM	Weida Semiconductor
WCMA2016U4X	128K x 16 STATIC	Weida Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar