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PDF ATA6829 Data sheet ( Hoja de datos )
| Número de pieza | ATA6829 | |
| Descripción | Dual Triple DMOS Output Driver | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Supply Voltage up to 40V
• RDSon Typically 0.5Ω at 25°C, Maximum 1.1Ω at 150°C
• Up to 1.5A Output Current
• Three High-side and Three Low-side Drivers Usable as Single Outputs or Half Bridges
• Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
• PWM Capability for Each Output Controlled by External PWM Signal
• No Shoot-through Current
• Very Low Quiescent Current IS < 5 µA in Standby Mode over Total Temperature Range
• Outputs Short-circuit Protected
• Selective Overtemperature Protection for Each Switch and Overtemperature
Prewarning
• Undervoltage Protection
• Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature
and Power-supply Fail Detection
• Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
• SO16 Power Package
www.DataSheet4U.com
Dual Triple
DMOS Output
Driver with
Serial Input
Control
1. Description
The ATA6829 is a fully protected driver interface designed in 0.8-µm BCDMOS tech-
nology. It is used to control up to six different loads by a microcontroller in automotive
and industrial applications.
Each of the three high-side and three low-side drivers is capable to drive currents up
to 1.5A. Each driver is freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined. The IC design especially supports the
applications of H-bridges to drive DC motors. The capability to control each output
with an external PWM signal opens additional applications.
Protection is guaranteed regarding short-circuit conditions, overtemperature and
undervoltage. Various diagnostic functions and a very low quiescent current in
stand-by mode opens a wide range of applications. Automotive qualification (protec-
tion against conducted interferences, EMC protection and 2-kV ESD protection) gives
added value and enhanced quality for exacting requirements of automotive
applications.
ATA6829
4531G–BCD–07/09
1 page  
ATA6829
www.DataSheet4U.co
Table 3-2. Output Data Protocol
Output (Status)
Bit
Register
Function
0 TP Temperature prewarning: high = warning
Normal operation: high = output is on, low = output is off
1
Status LS1
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched
off); not affected by SRR
Normal operation: high = output is on, low = output is off
2
Status HS1
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched
off); not affected by SRR
3
Status LS2
Description see LS1
4
Status HS2
Description see HS1
5
Status LS3
Description see LS1
6
Status HS3
Description see HS1
7 n. u. Not used
8 n. u. Not used
9 n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
Over-load detected: set high, when at least one output is switched off by
13
OVL
a short-circuit condition or an overtemperature event. Bits 1 to 6 can be
used to detect the affected switch.
(open-load detection bit OLD = high)
14
INH
Inhibit: this bit is controlled by software (bit SI in input register)
High = standby, low = normal operation
15 PSF Power-supply fail: undervoltage at pin VS detected
After power-on reset, the input register has the following status:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
SI OCS OLD PH3 PL3 PH2 PL2
Bit 8
PH1
Bit 7
PL1
HH H L L L L L L
Bit 6
HS3
L
Bit 5
LS3
L
Bit 4
HS2
L
Bit 3
LS2
L
Bit 2
HS1
L
Bit 1
LS1
L
Bit 0
SRR
L
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
(OCS)
Bit 8
Bit 7
Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3 Bit 2 Bit 1
(LS2) (HS1) (LS1)
Bit 0
(SRR)
HH H H H L L L L L L L L LL L
HH H L L H H L L L L L L LL L
HH H L L L L H H L L L L LL L
4531G–BCD–07/09
5
5 Page 
ATA6829
www.DataSheet4U.com
9. Serial Interface – Timing
No. Parameters
Test Conditions Pin Timing Chart No.(1) Symbol Min. Typ. Max. Unit Type*
8.1
DO enable after CS
falling edge
CDO = 100 pF
10
1
tENDO
200 ns
D
8.2
DO disable after CS
rising edge
CDO = 100 pF
10
2
tDISDO
200 ns
D
8.3 DO fall time
CDO = 100 pF
10
-
tDOf
100
8.4 DO rise time
CDO = 100 pF
10
-
tDOr
100
8.5 DO valid time
CDO = 100 pF
10
10
tDOVal
200
8.6 CS setup time
5
4
tCSSethl
225
8.7 CS setup time
5
8
tCSSetlh
225
8.8 CS high time
59
tCSh 500
8.9 CLK high time
75
tCLKh
225
8.10 CLK low time
76
tCLKl
225
8.11 CLK period time
7-
tCLKp
500
8.12 CLK setup time
7
7
tCLKSethl
225
8.13 CLK setup time
7
3
tCLKSetlh
225
8.14 DI setup time
6 11
tDIset
40
8.15 DI hold time
6 12
tDIHold
40
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
D
D
D
D
D
D
D
D
D
D
D
D
Note: 1. See Figure 9-1 on page 12
4531G–BCD–07/09
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ATA6829.PDF ] | |
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