|
|
Numéro de référence | KK74AC112 | ||
Description | Dual J-K Flip-Flop | ||
Fabricant | KODENSHI KOREA | ||
Logo | |||
TECHNICAL DATA
www.DataSheet4U.com
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
KK74AC112
The KK74AC112 is identical in pinout to the LS/ALS112,
HC/HCT112. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74AC112N Plastic
KK74AC112D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q
Q
LH
X XX H L
HL
LL
X XX L H
X X X L* L*
HH
L L No Change
HH
LH L
H
HH
HL H
L
HH
HH
Toggle
HH
L X X No Change
HH
H X X No Change
HH
X X No Change
* Both outputs will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
1
|
|||
Pages | Pages 6 | ||
Télécharger | [ KK74AC112 ] |
No | Description détaillée | Fabricant |
KK74AC11 | Triple 3-Input AND Gate High-Performance Silicon-Gate CMOS | KODENSHI KOREA |
KK74AC112 | Dual J-K Flip-Flop | KODENSHI KOREA |
US18650VTC5A | Lithium-Ion Battery | Sony |
TSPC106 | PCI Bus Bridge Memory Controller | ATMEL |
TP9380 | NPN SILICON RF POWER TRANSISTOR | Advanced Semiconductor |
www.DataSheetWiki.com | 2020 | Contactez-nous | Recherche |