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PDF ORSO42G5 Data sheet ( Hoja de datos )
| Número de pieza | ORSO42G5 | |
| Descripción | (ORSO42G5 / ORSO82G5) 0.6 to 2.7 Gbps SONET Backplane Interface FPSCs | |
| Fabricantes | Lattice Semiconductor | |
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ORCA® ORSO42G5 and ORSO82G5www.DataSheet4U.com
0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
July 2008
Data Sheet DS1028
Introduction
Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5
devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSO42G5 and
ORSO82G5 are high-speed transceivers with aggregate bandwidths of over 10 Gbps and 20 Gbps respectively.
These devices are targeted toward users needing high-speed backplane interfaces for SONET and other non-
SONET applications. The ORSO42G5 has four channels and the ORSO82G5 has eight channels of integrated 0.6-
2.7Gbps SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable
FPGA system gates. The CDR circuitry, available from Lattice’s high-speed I/O portfolio (sysHSI™), has already
been used in numerous applications to create STS-48/STM-16 and STS-192/STM-64 SONET/SDH interfaces.
With the addition of protocol and access logic, such as framers and Packet-over-SONET (PoS) interfaces, design-
ers can build a configurable interface using proven backplane driver/receiver technology. Designers can also use
the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. The
ORSO42G5 and ORSO82G5 can also be used to provide a full 10 Gbps backplane data connection and, with the
ORSO82G5, support both work and protection connections between a line card and switch fabric.
The ORSO42G5 and ORSO82G5 support a clockless high-speed interface for interdevice communication on a
board or across a backplane. The built-in clock recovery of the ORSO42G5 and ORSO82G5 allows higher system
performance, easier-to-design clock domains in a multiboard system and fewer signals on the backplane. Network
designers will benefit from using the backplane transceiver as a network termination device. Sister devices, the
ORT42G5 and the ORT82G5, support 8b/10b encoding/decoding and link state machines for 10 Gbit Ethernet
(XAUI) and Fibre Channel. The ORSO42G5 and ORSO82G5 perform SONET data scrambling/descrambling,
streamlined SONET framing, limited Transport OverHead (TOH) handling, plus the programmable logic to termi-
nate the network into proprietary systems. The cell processing feature in the ORSO42G5 and ORSO82G5 makes
them ideal for interfacing devices with any proprietary data format across a high-speed backplane. For non-SONET
applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. The
ORSO42G5 and ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices.
Table 1. ORCA ORSO42G5 and ORSO82G5 Family – Available FPGA Logic
Device
PFU
FPGA Max
PFU Rows Columns Total PFUs User I/O
LUTs
EBR
Blocks2
EBR Bits
(K)
FPGA
System
Gates (K)1
ORSO42G5
36
36
1296
204 10,368 12
111 333-643
ORSO82G5
36
36
1296
372 10,368 12
111 333-643
1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The System Gate
ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with
40% EBR usage and 2 PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80%
EBR usage and 4 PLLs.
2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.
.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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DS1028_08.0
1 page  
Lattice Semiconductor
ORCA ORSO42G5 and ORSOw8w2wG.D5atDaSahteaetS4Uh.ceoemt
• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over
previous architectures.
• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
faster routing times with predictable and efficient performance.
• Supplemental Logic and Interconnect Cell (SLIC) provides eight 3-statable buffers, up to a 10-bit decoder, and
PAL™-like AND-OR-Invert (AOI) in each programmable logic cell.
• New 200 MHz embedded block-port RAM blocks,
2 read ports, 2 write ports, and 2 sets of byte lane enables. Each embedded RAM block can be configured as:
– 1—512 x 18 (block-port, two read/two write) with optional built in arbitration.
– 1—256 x 36 (dual-port, one read/one write).
– 1—1K x 9 (dual-port, one read/one write).
– 2—512 x 9 (dual-port, one read/one write for each).
– 2 RAMS with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).
– Supports joining of RAM blocks.
– Two 16 x 8-bit Content Addressable Memory (CAM) support.
– FIFO 512 x 18, 256 x 36, 1Kx 9, or dual 512 x 9.
– Constant multiply (8 x 16 or 16 x 8).
– Dual variable multiply (8 x 8).
• Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI),
embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built-
in system registers that act as the control and status center for the device.
• Built-in testability:
– Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG).
– Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7.
– TS_ALL testability function to 3-state all I/O pins.
– New temperature-sensing diode.
• Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provide optimum clock
modification and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Multiplication of
the input frequency up to 64x and division of the input frequency down to 1/64x possible.
• New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route.
This feature also enables compliance with many setup/hold and clock to out I/O specifications and may provide
reduced ground bounce for output buses by allowing flexible delays of switching output buffers.
• PCI local bus compliant for FPGA I/Os.
Programmable Logic System Features
• Improved PowerPC ® 860 and PowerPC II high-speed synchronous MicroProcessor Interface can be used for
configuration, readback, device control, and device status, as well as for a general-purpose interface to the
FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors
with user-configurable address space provided.
• New embedded system bus facilitates communication among the MicroProcessor Interface, configuration logic,
Embedded Block RAM, FPGA logic, and embedded standard cell blocks.
• Variable size bused readback of configuration data with the built-in MicroProcessor Interface and system bus.
• Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.
• New clock routing structures for global and local clocking significantly increases speed and reduces skew.
• New local clock routing structures allow creation of localized clock trees.
• Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved
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Lattice Semiconductor
ORCA ORSO42G5 and ORSOw8w2wG.D5atDaSahteaetS4Uh.ceoemt
Figure 1. ORSO42G5 and ORSO82G5 Basic Chip Configuration
ORCA 4E04-Based
Programmable Logic
Embedded
Core
(4 or 8 Serial
Channels)
The ORSO42G5 and ORSO82G5 support aggregate bandwidths over 10Gbps and are targeted towards users
needing high-speed backplane interfaces for SONET and other non-SONET proprietary backplanes. For non-
SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is
required.
Built using Series 4 reconfigurable System-on-a-Chip (SoC) architecture, the ORSO42G5 and ORSO82G5 contain
the FPGA base array and an embedded core supporting eight serial data channels, with clock and data recovery
functions, and provides SONET framing, scrambling/descrambling and cell processing on a single monolithic chip
to enable high-speed asynchronous serial data transfer between system devices. Devices can be on the same PC-
board, on separate boards connected across a backplane or connected by cables. The ORSO42G5 and
ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices.
The ORSO42G5 and ORSO82G5 are considered pseudo-SONET devices because they do not support full over-
head processing, pointer processing or meet all SONET jitter/timing requirements. The ORSO42G5 and
ORSO82G5 are designed primarily for use as SONET backplane devices and not for network termination.
Although they format and process data as SONET frames, they cannot terminate data directly on a SONET ring
without additional functionality being implemented in the FPGA logic because the embedded core is not fully
SONET compliant on a stand-alone basis.
The ORSO42G5 and ORSO82G5 embedded cores support the following:
• Section/Line Overhead: A1/A2 (framing bytes), B1 (BIP-8), K2 (APS)
• Alarms: OOF (Out Of Frame), B1 error, RDI
• Two modes of automatic Transport OverHead (TOH) generation and insertion
• AIS-L insertion
• SPE signal generation which support +/- stuff events (but no pointer processing)
Embedded Core Overview
The functions in the embedded core portion of the ORSO42G5 and ORSO82G5 devices include:
• Eight channel 2.7 Gbps serializer/deserializer functions with Clock and Data Recovery (CDR).
• Eight-bit Interface to the Series 4 system bus for control and status information exchange.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ORSO42G5.PDF ] | |
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