PDF ORSPI4 Data sheet ( Hoja de datos )

Número de pieza	ORSPI4
Descripción	Dual SPI4 Interface and High-Speed SERDES FPSC
Fabricantes	Lattice Semiconductor
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No Preview Available ! ORCA ORSPI4ww®w.DataSheet4U.com Dual SPI4 Interface and High-Speed SERDES FPSC October 2007 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconﬁgurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b encoding and decoding and over 600K programmable system gates all on a single chip. Embedded SPI4 Core Features ■ OIF-SPI4-02.0 compliant interfaces ■ Dynamic timing receive interface: • Full bandwidth up to 450 MHz DDR (900 Mbits/s) for all speed grades. • Bit de-skewing up to 16 phases of the clock • Capable of aligning bit-to-bit skews as large as ±1 bit periods ■ Static timing receive interface: • Speeds up to 325 MHz DDR (650 Mbits/s), for all speed grades, including Quarter-Rate mode • Clock aligned or clock centered modes sup- ported ■ DIP-4 and DIP-2 parity generation and checking ■ Transmit Interface: • Speeds up to 450 MHz DDR (900 Mbits/s) • Dedicated LVDS transmit interface for improved data eye integrity • Automatic idle insertion ■ 256 logical ports: • Embedded Calendar-based sequence port poll- ing mechanism and bandwidth allocation. Shadow Calendar support for smooth transition to new Calendar • Up to 32 independent TX and 32 independent RX buffers per SPI4 interface internally. Various aggregation modes to support 1 to 32 separate embedded buffers per TX and RX • Up to 4 independent TX and 4 independent RX clock domain transfers to the FPGA logic ■ FIFO status support modes: • 1/4 rate LVTTL or 1/4 rate LVDS • Automatic status handling or optionally under user control. Credit calculations based on burst size and status are also handled automatically ■ Conﬁguration options as suggested in the OIF- SPI4-02.0 standard • Conﬁgures parameters such as maximum burst size, calendar length, main and shadow calen- dars (1K deep each), length of training sequence etc. ■ Simple FIFO interface to the FPGA logic • Provides ease of design and efﬁcient clock domain transfers ■ Loopback modes provided for system- and chip-level debug ■ Embedded 32-bit internal system bus plus 4-bit parity • Interconnects FPGA logic, microprocessor inter- face (MPI), embedded RAM blocks, and embed- ded core blocks • Includes built-in system registers that act as the control and status center for the device ■ Low power operation. • Full-rate SPI4.2 interfaces running at 450 MHz DDR (900 Mbits/sec) with dynamic alignment consumes 1.5 W of power or less. More efﬁcient than FPGAs with soft-IP SPI4 solutions which consume in excess of 10 W. ■ Programmable Minburst capability with selectable burst values ranging from 16 to 240. ■ Interoperability demonstrated with ORSPI4 partners. Embedded SERDES Core Features ■ Quad 600 Mbits/s to 3.7 Gbits/s SERDES: • IEEE 802.3ae XAUI (Link State Machine & Alignment FIFOs embedded) • ANSI X3.230:1994 1G/2G FC-compliant (Link State Machine & Alignment FIFOs embedded) • Proven performance (same SERDES used in ORT82G5/ORT42G5 FPSCs) Embedded Memory Controller Features ■ High Performance Memory Controller for interface to external buffer memory • Required for Layer 2 data buffering • QDR II memory interface: – 36-bit Input and 36-bit Output bus, 18-bit address – 175 MHz clock rates – 20+ Gbits/s bandwidth – Supports 2- or 4-word burst mode – Simple FIFO interface to FPGA – Integrated PLL for optimized performance – Proven performance with multiple memory suppliers Note: The term SPI4 refers to OIF SPI-4.2 throughout this document © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice. www.latticesemi.com 1 ORSPI4_06 1 page Lattice Semiconductor Figure 2. System Model for SPI4 Interface Link Layer in Model Transmit Link Layer Device TSTAT[1:0] TSCLK TDCLK TDAT[15:0] TCTL Receive Link Layer Device RSTAT[1:0] RSCLK RDCLK RDAT[15:0] RCTL ORCA ORwSwPw.ID4atDaSahteaetS4Uh.ceoemt PHY Layer in Model Physical (PHY) Layer Device The details of the interface are speciﬁed in the OIF document “Implementation Agreement OIF-SPI4-02.0” (www.oiforum.com). That speciﬁcation is based on the system model shown in the previous ﬁgure, which, in turn, is based on the Open System Interconnect (OSI) reference model. In the system model, a “transmit interface” sends address, start and end of packet signals and error control information from a Link Layer device to a PHY device and receives ﬂow control (status) information from the PHY device. In the other direction, a “receive interface” at the Link Layer receives data from a PHY device and sends status information to the PHY device. While this convention provides a clear framework for deﬁning the system level functions, a clean separation between Link Layer and Physical Layer functionality is not often seen in actual implementations. The ORSPI4 FPSC SPI4 blocks implement the basic functions deﬁned in the standard and also implements addi- tional options, as suggested in the standard, to conﬁgure parameters such as maximum burst size, calendar length, length of training sequence, etc. As required by the speciﬁcation, the transmit and receive interfaces oper- ate completely independently. 5 5 Page Lattice Semiconductor ORCA ORwSwPw.ID4atDaSahteaetS4Uh.ceoemt which corresponds to the maximum number of ports that are supported by SPI4. The PDM data is comprised of three separate segments - a 10-bit dynamic table maintained by the SPI4 logic, a static 20-bit table, and a dynamic 3-bit register ﬁle written by the FIFO Status Update (FSU) logic. The PDM provides a mapping of the SPI4 port number to the FPGA interface device/port number, removing the burden from FPGA logic. When port data is read from the PDM, a status update bit (the U-bit) is ﬁrst examined to see whether the STAT ﬁeld is new or stale. If stale, then the STAT ﬁeld is not considered for the rest of processing. If the STAT ﬁeld is new (U- bit=1) the STAT ﬁeld is used in conjunction with other ﬁeld to calculate what the new Credit ﬁeld for the port should be. A SATISFIED status indicates the corresponding port's FIFO is almost full, and only transfers using the remaining previously granted 16-byte blocks (if any) may be sent to corresponding port until the next status update. No addi- tional transfers to that port are permitted. When a HUNGRY status indication is received, transfers up to MAXBURST2 16-byte blocks or the remainder of what was previously granted (whichever is greater), may be sent to the corresponding port prior to the next status update. A STARVING status indication indicates that buffer underﬂow is imminent in the corresponding PHY port. When STARVING is received, transfers for up to MAXBURST1 16-byte blocks may be sent to the corresponding port prior to the next status update. If the U-bit is cleared, this indicates the STAT ﬁeld has already been used to update the Credit ﬁeld on a previous Port servicing. Therefore, the Credit ﬁeld should simply be reduced by BURST_VAL. Otherwise, the Credit ﬁeld is updated to the new Credit value minus BURST_VAL. In both cases, the output of the logic is used to update the Credit ﬁeld. If the Credit ﬁeld is zero, and the STAT ﬁeld is stale, then the port receives no service. Read accesses of the port control information need to be optimized to minimize any lost bandwidth due to the Credit ﬁeld having a value of zero. Data read from the DPRAMS is sent to the SPI4 transmit block which is responsible for the following functions: • Combining the data and control words from the Transmit FIFO into the data format speciﬁed in the OIF SPI4 standard. • DIP-4 calculation and insertion into the payload control word. • Generation of idle/training control words in programmable intervals. Training words are used to dynamically align the far end receiver. As long as a disabled status ‘11’ is received on the SPI4 status channel, the transmit interface block sends continuous training patterns (10 training control words followed by 10 training data words). When valid status is received on the status channel, user data is normally sent on the SPI4 data link. However, users can also periodically schedule training patterns in TX_DATA_MAX_T peri- ods. The training patterns can be repeated TX_ALPHA times. Both TX_ALPHA and TX_DATA_MAX_T are pro- grammable control register bits. The SPI4 transmit block contains the high-speed serializer which uses the x8 clock, synthesized by an internal PLL, to generate the high-speed data from the low-speed 128-bit FIFO data. Data is transmitted off-chip using a 16-bit LVDS data bus - TDAT[15:0], a LVDS control bit - TCTL, and a source synchronous clock - TDCLK. The 16-bit data bus and control are DDR with respect to TDCLK. In order to support 10 Gbits/s throughput, the minimum frequency of TDCLK needs to be 622 Mbits/s (311 MHz DDR). To allow considerable margin above this minimum data rate a maximum frequency of operation of 900 Mbits/s is supported. The Transmit Status Protocol (S4TSP) block provides the interface to the SPI4 Transmit Status interfaces. These signals can be either LVDS or LVCMOS buffers. The S4TSP block is responsible for the following functions: • FIFO Status Decoding and Buffering. • Framing using the status framing pattern. • DIP-2 checking of incoming status information. 11 11 Page

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