ZL2008 Datasheet PDF - Intersil Corporation
| Part Number | ZL2008 | |
| Description | Digital DC-DC Controller | |
| Manufacturers | Intersil Corporation | |
| Logo |  |
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Data Sheet
ZL2008
www.DataSheet4U.com
February 19, 2009
FN6859.0
Digital DC-DC Controller with Drivers and Pin-Strap Current Sharing
Description
The ZL2008 is a digital DC-DC controller with
integrated MOSFET drivers. Current sharing allows
multiple devices to be connected in parallel to source
loads with very high current demands. Adaptive
performance optimization algorithms improve power
conversion efficiency. Zilker Labs Digital-DC™
technology enables a blend of power conversion
performance and power management features.
The ZL2008 is designed to be a flexible building block
for DC power and can be easily adapted to designs
ranging from a single-phase power supply operating
from a 3.3 V input to a multi-phase supply operating
from a 12 V input. The ZL2008 eliminates the need for
complicated power supply managers as well as
numerous external discrete components.
Key operating features can be configured by pin-straps,
including compensation, current sharing and output
voltage. The ZL2008 uses the I2C/SMBus™ with
PMBus™ protocol for communication with a host
controller and the Digital-DC bus for communication
between Zilker Labs devices.
Features
Power Conversion
Efficient synchronous buck controller
Adaptive light load efficiency optimization
3 V to 14 V input range
0.54 V to 5.5 V output range (with margin)
POLA and DOSA voltage trim modes
±1% output voltage accuracy
Internal 3 A MOSFET drivers
Fast load transient response
Current sharing and phase interleaving
Snapshot™ parameter capture
RoHS compliant (6 x 6 mm) QFN package
Power Management
Digital soft start / stop
Precision delay and ramp-up
Power good / enable
Voltage tracking, sequencing and margining
Voltage, current and temperature monitoring
I2C/SMBus interface, PMBus compatible
Output voltage and current protection
Internal non-volatile memory (NVM)
Applications
Servers / storage equipment
Telecom / datacom equipment
Power supply modules
EN PG PH_EN FC ILIM CFG UVLO V25 VR VDD
V
SS
VTRK
MGN
SYNC
DDC
SCL
SDA
SALRT
POWER
MANAGEMENT
NON-
VOLATILE
MEMORY
I2 C
PWM
CONTROLLER
MONITOR
ADC
LDO
DRIVER
CURRENT
SENSE
TEMP
SENSOR
BST
GH
SW
GL
VSEN+
VSEN-
ISENA
ISENB
SA
XTEMP
PGND SGND DGND
Figure 1. Block Diagram
Figure 2. Efficiency vs. Load Current
1 1-888-INTERSIL or 1-888-468-3774|Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners
|
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ZL2008
Table 3. Electrical Specifications
VDD = 12 V, TA = -40°C to 85°C unless otherwise noted. Typical values are at TA = 25°C.
www.DataSheet4U.com
Parameter
Conditions
Min Typ Max Unit
Input and Supply Characteristics
IDD supply current at fSW = 200 kHz
IDD supply current at fSW = 1.4 MHz
IDDS shutdown current
VR reference output voltage
V25 reference output voltage
GH, GL no load;
MISC_CONFIG[7] = 1
EN = 0 V
No I2C/SMBus activity
VDD > 6 V, IVR < 50 mA
VR > 3 V, IV25 < 50 mA
– 16 30 mA
– 25 50 mA
– 6.5 8 mA
4.5 5.2 5.5
2.25 2.5 2.75
V
V
Output Characteristics
Output voltage adjustment range1
Output voltage set-point resolution
Output voltage accuracy3
VSEN input bias current
Current sense differential input
voltage (ground referenced)
Current sense differential input
voltage (VOUT referenced,
VOUT < 4.0 V)
Current sense input bias current
Current sense input bias current
(VOUT referenced, VOUT < 4.0 V)
Soft start delay duration range4
VIN > VOUT
Set using resistors
Set using I2C/SMBus
Includes line, load, temp
VSEN = 5.5 V
VISENA - VISENB
VISENA - VISENB
Ground referenced
ISENA
ISENB
Set using SS pin or resistor
Set using I2C/SMBus
0.6
–
–
-1
–
- 100
–
10
±0.025
–
110
–
- 50
- 100
-1
- 100
2
0.002
–
–
–
–
–
–
5.0
–
–
1
200
100
50
100
1
100
30
500
V
mV
% FS2
%
µA
mV
mV
µA
µA
µA
ms
s
Soft start delay duration accuracy
Turn-on delay (precise mode) 4,5
Turn-on delay (normal mode) 6
Turn-off delay 6
–
–
–
±0.25
-0.25/+4
–
-0.25/+4
–
–
ms
ms
ms
Soft start ramp duration range
Set using SS pin or resistor
Set using I2C
2 – 20 ms
0 – 200 ms
Soft start ramp duration accuracy
– 100 –
µs
Notes:
1. Does not include margin limits.
2. Percentage of Full Scale (FS) with temperature compensation applied.
3. VOUT measured at the termination of the VSEN+ and VSEN- sense points.
4. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this
delay period to approx 2 ms, where in normal mode it may vary up to 4 ms.
5. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.
6. The devices may require up to a 4 ms delay following the assertion of the enable signal (normal mode) or following the de-
assertion of the enable signal.
5 Data Sheet Revision 2/19/2009
www.intersil.com
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ZL2008 electronic component. |
| Information | Total 30 Pages | |
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