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PDF LP1072 Data sheet ( Hoja de datos )
| Número de pieza | LP1072 | |
| Descripción | 802.11a/b/g Baseband System Solution | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LP1072 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Freescale Semiconductor
Advance Information
Document Number: LP1072
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LP1072
802.11a/b/g Baseband System
Solution
1 Introduction
1.1 The LP1070 Family
Freescale Semiconductor’s 802.11 LP1070 family
consists of high-performance, highly optimized PHY
and MAC baseband Wireless LAN processors that fully
implement the IEEE 802.11a, 802.11b and 802.11g PHY
standards. These baseband processors are poised to
revolutionize the Wireless LAN industry by setting new
standards for power consumption, size, cost and
performance.
The LP1070 family is based on Freescale's proprietary
Wireless Broadband Signal Processor™ (WBSP™), an
innovative and revolutionary receiver architecture that
significantly reduces size and power consumption while
providing maximum flexibility to support multiple
wireless standards with no additional overhead.
In addition to their superior performance and ultra low
power consumption, the LP1070 processors provide the
customers with the flexibility to tailor the chip
characteristics to their needs. With software control, the
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Functional Description . . . . . . . . . . . . . . . . . 4
4 LP1072 Interfaces . . . . . . . . . . . . . . . . . . . . . 10
5 Timers/Reset . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Pinout and Footprint . . . . . . . . . . . . . . . . . . 17
7 DC Electrical Specifications . . . . . . . . . . . . 24
8 Timing Characteristics . . . . . . . . . . . . . . . . . 26
9 Mechanical Dimensions . . . . . . . . . . . . . . . . 29
10 Development Support . . . . . . . . . . . . . . . . . 29
11 Appendix: Comparison of LP1071 and
LP1072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12 Revision History . . . . . . . . . . . . . . . . . . . . . 31
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
PRELIMINARY
1 page  
3.1.1 UART
Functional Description
www.DataSheet4U.com
The UART is used for testing and diagnostic purposes and is capable of supporting data transfer rates of
up to 115.2 kbps.
3.1.2 JTAG
TBA
3.1.3 Serial EEPROM Interface
The LP1072 supports an external serial EEPROM for storing the boot loader, MAC address, calibration
data and any other vendor-specific data. The LP1072 supports serial EEPROMs of sizes from 8 Kbit
(organized as 1024 entries of 8 bits each, or 1024 x 8) up to 512 Kbit (organized as 65,536 x 8). Serial
EEPROMs from the following vendors have been tested and verified to work with the LP1072:
• ATMEL (http:/www.atmel.com)
• ST Microelectronics (http://www.st.com)
• Microchip Technology (http://www.microchip.com)
• Catalyst Semiconductor (http://www.catsemi.com)
• Integrated Silicon Solutions, Inc. (http://www.issi.com)
The EEPROM is supported through GPIOs. There is no dedicated hardware to support either I2C or SPI
serial EEPROMs.
The operating frequency of the serial EEPROM port is 400 kHz with a supply voltage of 3.0 V.
3.1.4 GPIO
To support vendor-specific needs, the LP1072 provides eight bi-directional General Purpose Input Output
(GPIO) pins. Each pin can be independently configured as an input, output or an interrupt source. On reset,
the GPIOs default as inputs, i.e. output drivers enables will be inactive.
3.1.5 RMB Registers
This block contains all the reset logic for both CPUs contained in the BRC and chip-wide reset control. It
also defines controls for memory address re-mapping.
3.1.6 Watchdog
TBA
3.1.7 Interrupt Controller
TBA
Freescale Semiconductor
LP1072 Advance Information, Rev. 0.3
PRELIMINARY
5
5 Page 
• Combo Card (I/O mode only)
LP1072 Interfaces
www.DataSheet4U.com
4.1.2 SDIO Function 0/1
For Function 0 registers descriptions, refer to SDIO Card Specification. For Function 1, the SDIO registers
occupy a 128 Kbyte space as defined in the SDIO specification. Figure 2 illustrates SDIO Function 1
128 Kbyte Memory Map and Table 8 details its registers.
Bit7
0x0000 Reserved
Bit0
0x0015 Reserved
0x0016 Reserved
0x0017
0x0018
0x001C
ARM to Host Interrupt
Enable register 0
ARM to Host Interrupt
Enable register 1
SDIO Mailbox semaphore 0
0x001D SDIO Mailbox semaphore 1
0x000E Watchdog Reset Register
0x000F SDIO Host to Device
Interrupt Register 0
0x0010 Reserved
0x0011 Reserved
0x0012 Reserved
0x0013
0x0014
ARM to Host Interrupt
Source register 0
ARM to Host Interrupt
Source register 1
0x001E SDIO Mailbox semaphore 2
0x0020
Reserved
0x1FFF
0x2000 2 KByte Mailbox
space
RAM0
RAM1
0x27FF
0x2800
Reserved
0x3FFF
0x4000
RAM2
0x200E
0x200F
0x23FF
0x2400
8Kbyte Internal Memory
0x5FFF
Figure 2. SDIO Function 1 128 Kbyte Memory Map
Freescale Semiconductor
LP1072 Advance Information, Rev. 0.3
PRELIMINARY
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LP1072.PDF ] | |
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