WC32P040-XXM Datasheet PDF - White Electronic Designs Corporation
| Part Number | WC32P040-XXM | |
| Description | 32-Bit Nonmultiplexed External Address and Data Buses | |
| Manufacturers | White Electronic Designs Corporation | |
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White Electronic Designs
WC32P040-XXM
www.DataSheet4U.com
68040 FEATURES
Selection of Processor Speeds: 25, 33MHz
Military Temperature Range: -55°C to +125°C
Packaging
• 179 pin Ceramic PGA (P4)
• 184 lead Ceramic Quad Flatpack, CQFP (Q4)
6-Stage Pipeline, 68030-Compatible IU
68881/68882-Compatible FPU
Independent Instruction and Data MMUs
Simultaneously Accessible, 4-Kbyte Physical
Instruction Cache and 4-Kbyte Physical Data Cache
Low-Latency Bus Acceses for Reduced Cache Miss
Penalty
Multimaster/Multiprocessor Support via Bus
Snooping
Concurrent IU, FPU, MMU, and Bus Controller
Operation Maximizes Throughput
32-Bit, Nonmultiplexed External Address and Data
Buses with Synchronous Interface
User Object-Code Compatible with all Earlier 68000
Microprocessors
4-GigaByte Direct Addressing Range
DESCRIPTION
The WC32P040 is a 68000-compatible, high-performance,
32-bit microprocessor. The WC32P040 is a virtual
memory microprocessor employing multiple concurrent
execution units and a highly intergrated architecture that
provides very high performance in a monolithic HCMOS
device. It has a 68030-compatible integer unit (IU) and
two independent caches. The WC32P040 contains dual,
independent, demand-paged memory management units
(MMUs) for instruction and data stream accesses and
independent, 4-Kbyte instruction and data caches. The
WC32P040 has a 68881/68882-compatible floating-point
unit (FPU).
FIGURE 1 – BLOCK DIAGRAM
INSTRUCTION DATA BUS
CONVERT
EXECUTE
WRITE-
BACK
FLOATING-
POINT
UNIT
INSTRUCTION
FETCH
DECODE
EA
CALCULATE
EA
FETCH
EXECUTE
WRITE-
BACK
INTEGER
UNIT
INSTRUCTION
ATC
INSTRUCTION
CACHE
INSTRUCTION
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION MEMORY UNIT
INSTRUCTION
ADDRESS
DATA MEMORY UNIT
DATA
MMU/CACHE/SNOOP
CONTROLLER
DATA
ADDRESS
B
U
S
C
O
N
T
R
O
L
L
E
R
DATA
ATC
DATA
CACHE
ADDRESS
BUS
DATA
BUS
BUS
CONTROL
SIGNALS
JJuulyly19199898
OPERAND DATA BUS
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic Designs
WC32P040-XXM
www.DataSheet4U.com
Opcode
ASL,ASR
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST
CAS
CAS2
CHK
CHK2
CINV
CLR
CMP
CMPA
CMPI
CMPM
CMP2
CPUSH
July 1998
INSTRUCTION SET SUMMARY (contd)
Operation
Destination Shifted by count Destination
It condition true
then PC + dn PC
~(bit number of Destination) Z;
~(bit number ot Destination) (bit number) of Destination
~(bit number ot Destination) Z;
0 bit number ot Destination
~(bit field ot Destination) bit field of Destination
0 bit field of Destination
bit field of Source Dn
bit offset of Source Dn
bit offset of Source Bit Scan Dn
Dn bit field of Destination
1s bit field of Destination
bit field of Destination
Run breakpoint acknowledge cycle; TRAP as illegal instruction
PC+dn PC
~(bit number ot Destination) Z;
1 bit number of Destination
SP - 4 SP; PC (SP); PC + dn PC
–(bit number of Destination) Z
CAS Destination – Compare Operand cc;
if Z, Update Operand Destination
else Destination Compare Operand
CAS2 Destination 1 – Compare 1 cc;
if Z, Destination 2 – Compare cc;
if Z, Update 1 Destination 1;
Update 2 Destination 2
else Destination 1 Compare 1;
Destination 2 Compare 2
If Dn < 0 or Dn > Source then TRAP
If Rn < LB or If Rn > UB then TRAP
If supervisor state
then invalidate selected cache lines
else TRAP
0 Destination
Destination – Source cc
Destination – Source
Destination – Immediate Data
Destination – Source cc
Compare Rn < LB or Rn > UB and Set Condition Codes
If supervisor state
then it data cache push selected dirty data cache lines;
invalidate selected cache lines
else TRAP
Syntax
ASd Dx,Dy(1)
ASd #<data>,Dy(1)
ASd <ea>(1)
Bcc <label>
BCHG Dn,<ea>
BCHG #<data>,<ea>
BCLR Dn,<ea>
BCLR #<data>,<ea>
BFCHG <ea> {offset:width}
BFCLR <ea> {offset:width}
BFEXTS <ea> {offset:width}, Dn
BFEXTU <ea> {offset:width}, Dn
BFFFO <ea> {offset:width}, Dn
BFINS Dn,<ea> {offset:width}
BFSET <ea> {offset:width}
BFTST <ea> {offset:width}
BKPT #<data>
BRA <label>
BSET Dn,<ea>
BSET #<data>,<ea>
BSR <label>
BTST Dn,<ea>
BTST #<data>,<ea>
CAS Dc,Du,<ea>
CAS2 Dc1-Dc2,Du1-Du2,(Rn1)-(Rn2)
CHK <ea>,Dn
CHK2 <ea>,Rn
CINVL <caches>,
(An) CINVP <caches>,
(An) CINVA <caches>
CLR <ea>
CMP <ea>,Dn
CMPA <ea>,An
CMPI #<data>,<ea>
CMPM (Ay)+,(Ax)+
CMP2 <ea>,Rn
CPUSHL <caches>, (An)
CPUSHP <caches>, (An)
CPUSHA <caches>
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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| Information | Total 23 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ WC32P040-XXM.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| WC32P040-XXM | The function is 32-Bit Nonmultiplexed External Address and Data Buses. White Electronic Designs Corporation | |
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