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PDF AT90PWM216 Data sheet ( Hoja de datos )
| Número de pieza | AT90PWM216 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Atmel 8-bit Microcontroller with
16K Bytes In-System Programmable Flash
AT90PWM216 /AT90PWM316
Features
• High Performance, Low Power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 129 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1 MIPS throughput per MHz
– On-chip 2-cycle Multiplier
• Data and Non-Volatile Program Memory
– 16K Bytes Flash of In-System Programmable Program Memory
• Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– 512 Bytes of In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 1024 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
• On Chip Debug Interface (debugWIRE)
• Peripheral Features
– Two or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bit Resolution Enhancement
• Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time
• Variable PWM duty Cycle and Frequency
• Synchronous Update of all PWM Registers
• Auto Stop Function for Event Driven PFC Implementation
• Less than 25Hz Step Width at 150kHz Output Frequency
• PSC2 with four Output Pins and Output Matrix
– One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture Mode
– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture
Mode
– Programmable Serial USART
• Standard UART mode
• 16/17 bit Biphase Mode for DALI Communications
– Master/Slave SPI Serial Interface
– 10-bit ADC
• Up To 11 Single Ended Channels and 2 Fully Differential ADC Channel Pairs
• Programmable Gain (5x, 10x, 20x, 40x on Differential Channels)
• Internal Reference Voltage
– 10-bit DAC
– Two or three Analog Comparator with Resistor-Array to Adjust Comparison Voltage
– 4 External Interrupts
– Programmable Watchdog Timer with Separate On-Chip Oscillator
• Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power Down Modes
– Power On Reset and Programmable Brown Out Detection
– Flag Array in Bit-programmable I/O Space (4 bytes)
– In-System Programmable via SPI Port
– Internal Calibrated RC Oscillator (8 MHz)
– On-chip PLL for fast PWM (32 MHz, 64 MHz) and CPU (16 MHz)
• Operating Voltage: 2.7V - 5.5V
• Extended Operating Temperature:
– -40°C to +105°C
7710H–AVR–07/2013
1 page  
2.1 Pin Descriptions
Table 2-1. Pin out description
S024 Pin
Number
SO32 Pin
Number
QFN32 Pin
Number
795
18 24 20
684
Mnemonic
GND
AGND
VCC
17 23 19 AVCC
19 25 21 AREF
8 12 8 PBO
9 13 9 PB1
16 20 16 PB2
20 27 23 PB3
21 28 24 PB4
22 30 26 PB5
23 31 27 PB6
24 32 28 PB7
2 30 PC0
7 3 PC1
10 6 PC2
11
NA
7 PC3
21 17 PC4
22 18 PC5
26 22 PC6
29 25 PC7
Type
Power
Power
power
Power
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Name, Function & Alternate Function
Ground: 0V reference
Analog Ground: 0V reference for analog part
Power Supply:
Analog Power Supply: This is the power supply voltage for analog part
For a normal use this pin must be connected.
Analog Reference: reference for analog converter. This is the reference
voltage of the A/D converter. As output, can be used by external analog
MISO (SPI Master In Slave Out)
PSCOUT20 output
MOSI (SPI Master Out Slave In)
PSCOUT21 output
ADC5 (Analog Input Channel5)
INT1
AMP0- (Analog Differential Amplifier 0 Input Channel )
AMP0+ (Analog Differential Amplifier 0 Input Channel )
ADC6 (Analog Input Channel 6)
INT 2
ADC7 (Analog Input Channel 7)
ICP1B (Timer 1 input capture alternate input)
PSCOUT11 output (see note 1)
PSCOUT01 output
ADC4 (Analog Input Channel 4)
SCK (SPI Clock)
PSCOUT10 output (see note 1)
INT3
PSCIN1 (PSC 1 Digital Input)
OC1B (Timer 1 Output Compare B)
T0 (Timer 0 clock input)
PSCOUT22 output
T1 (Timer 1 clock input)
PSCOUT23 output
ADC8 (Analog Input Channel 8)
AMP1- (Analog Differential Amplifier 1 Input Channel)
ADC9 (Analog Input Channel 9)
AMP1+ (Analog Differential Amplifier 1 Input Channel)
ADC10 (Analog Input Channel 10)
ACMP1 (Analog Comparator 1 Positive Input)
D2A : DAC output(2)
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
5
5 Page 
ands are output from the Register File, the operation is executed, and the result is stored back in the Register File
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM (Store Program Mem-
ory) instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before sub-
routines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher is the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Reg-
ister File, 0x20 - 0x5F. In addition, the AT90PWM216/316 has Extended I/O space from 0x60 - 0xFF in SRAM
where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
4.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-
functions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
4.4 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
11
11 Page | ||
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| PDF Descargar | [ Datasheet AT90PWM216.PDF ] | |
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