PDF ATU18 Data sheet ( Hoja de datos )

Número de pieza	ATU18
Descripción	0.18um ULC Series with Embedded DPRAM
Fabricantes	ATMEL Corporation
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Features • High Performance ULC Family Suitable for Latest CPLDs and FPGAs conversion • Very effective associated Physical synthesis/optimization Flow • From 45K Gates up to 1000K Gates Supported • From 55Kbit to 847Kbit DPRAM • Compatible with Xilinx and Altera Latest FPGA’s • Pin-count: Over 700 pins • VDD 1.8V +/- 0.15V for core; 1.8V, 2.5V, 3.3V for Periphery • Any Pin–out Matched • Full Range of Packages: PQFP/TQFP/VQFP, BGA/FLBGA, PGA/PPGA, QFN, CS • Available in Commercial, Industrial and Military Grades • 0.18 um Drawn CMOS, 5 Metal Layers • Library Optimised for best Synthesis, Place & route and Testability Generation (ATPG) • High system clock Skew Control • 250Mhz system clock, up to 400Mhz for local clock • Power on Reset, PLL, Multiplier • Standard 3, 6, 12, 24 mA I/Os • LVCMOS, LVTTL, GTL, HSTL, LVPECL, PCI & LVDS Interfaces • High Noise & EMC Immunity • Thick Oxide periphery Allowing Interface with 2.5V and 3.3V Environments Description The ATU18 series of ULCs are fully suited for conversion of latest CPLDs and FPGAs. It supports within one ULC 55Kbits to 847Kbits DPRAM and 45Kgates to 1000 Kgates. Typically, ULC die size is 50% smaller than the equivalent FPGA. Metal level customisation allows a DPRAM blocks compatibility with Xilinx® or Altera® blocks. Devices are implemented in high–performance 0.18 um CMOS technology to improve the design frequency and reach 250Mhz typical application and local clock up to 400Mhz. The architecture of the ATU18 series is dedicated for efficient conversion of latest CPLD and FPGA device types with higher IO count. A compact RAM cell and a large number of available gates allow the implementation of memories compatible with FPGA RAM, as well as JTAG boundary–scan and scan–path testing. Conversion to the ATU18 series of ULC provides a significant reduction of the operat- ing power when compared to the original PLD or FPGA. The ATU18 series has a very low standby consumption, less than 0.145 nA/gate typically at commercial tempera- ture. Operating consumption is a strict function of clock frequency, which typically results in a significant power reduction depending on the device being compared. For a NAND2 cell the dynamic power consumption is 0.124uW/MHz at 1.8V. www.DataSheet4U.com 0.18 um ULC Series with Embedded DPRAM ATU18 4318C–ULC–08/05 1 page I/O Buffer Interfacing I/O Flexibility ATU18 www.DataSheet4U.com All I/O buffers at the periphery may be configured as input, output, bi-directional and oscillator. The IO power rings can be modified to allow clusterization (i.e. cluster at 1.8V cluster at 3.3V). When core supply differs from periphery supply, level shifters are available in IO buffers, for example in the following conditions: 3.3V I/O -> 1.8V core, 2.5V I/O->1.8V core. Each LVTTL, LVCMOS, or Schmitt Trigger input can be programmed with or without a pull up or pull down resistor or bus keeper. The Standard IO supported are given in table 3. Fast Output Buffer are able to drive 3 to 24mA at 3.3V according to the chosen option. (higher drive is achievable using two adjacent pads). Table 3. Standard IO Supported Standard IO LVTTL LVCMOS PCI33 PCI66 GTL GTL+ HSTL I, II, III, IV SSTL2 I, II SSTL3 LVPECL LVDS Comment 3.3V ( 3 to 24 mA) 1.8V/2.5V/3.3V ( 3 to 24 mA) 3.3V 3.3V 3.3V 3.3V input only input only input only input only 3.3V 4318C–ULC–08/05 5 5 Page Electrical Characteristics Absolute Maximum Ratings* Operating Temperature Commercial..........................................................0° to 70°C Industrial............................................................-40° to 85°C Military...............................................................-55° to 125°C Max Supply Core Voltage (VDD)..........................1.95 V Max Supply Periphery Voltage (VCC)...................3.6V 3.3V Tolerant/Compliant.....................................Vcc +0.3V Pad pullup resistor.............................................100Kohms Pad pulldown resistor........................................100Kohms Output buffer drive range....................................3 to 24 mA leakage current at Temp=25C..............................0.145nA/gate NAND2 dynamic power consumption......0.124uW/MHz at 1.8V Storage Temperature...........................................-65° to 150°C PLL Specifications Operating Modes - Clock tree reduction - Zero delay buffer - Phase shift - Frequency synthesis VCO range ..........................................66Mhz to 500Mhz OUT1, OUT2 output range..................66Mhz to 500 Mhz OUTX0, OUTX180 ouput range............33Mhz to 250 Mhz OUT0,90,180,270 output range...........16.5Mhz to 125Mhz VDDPLL supply ...................................1.8V +- 10% ATU18 www.DataSheet4U.com *NOTICE: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. This value is based on the maximum allowable die temperature and the thermal resistance of the package. 4318C–ULC–08/05 11 11 Page

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