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QuickLogic Corporation - PLD Gate pASIC 3 FPGA Combining High Performance and High Density

Numéro de référence QL3060
Description PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Fabricant QuickLogic Corporation 
Logo QuickLogic Corporation 





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QL3060 fiche technique
QL3060 pASIC 3 FPGA Data Sheet
• • • • • • 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
Device Highlights
High Performance & High Density
60,000 Usable PLD Gates with 316 I/Os
www.DataS3h0ee0t4MU.cHozm16-bit Counters,
400 MHz Datapaths
0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
Easy to Use / Fast Development
Cycles
100% routable with 100% utilization and
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high
quality Verilog/VHDL synthesis
Eight Low-Skew Distributed
Networks
Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
Six global clock/control networks available
to the logic cell F1, clock set, and reset
inputs and the input and I/O register clock,
reset, and enable inputs as well as the output
enable control — each driven by an input-
only or I/O pin, or any logic cell output or
I/O cell feedback
High Performance
Input + logic cell + output total delays
under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
Advanced I/O Capabilities
Interfaces with both 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 316 I/O Pins
308 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
Eight high-drive input/distributed
network pins
Figure 1: 1,584 pASIC 3 Logic Cells
© 2002 QuickLogic Corporation
www.quicklogic.com
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