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QuickLogic Corporation - PLD Gate pASIC 3 FPGA Combining High Performance and High Density

Numéro de référence QL3006
Description PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Fabricant QuickLogic Corporation 
Logo QuickLogic Corporation 





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QL3006 fiche technique
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‡ 6,000 Usable PLD Gates with 82 I/Os
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400 MHz Datapaths
‡ 0.35 µm four-layer metal non-volatile CMOS
process for smallest die sizes
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‡ 100% routable with 100% utilization and
complete pin-out stability
‡ Variable-grain logic cells provide high
performance and 100% utilization
‡ Comprehensive design tools include high
quality Verilog/VHDL synthesis
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‡ Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
‡ Two global clock/control networks available
to the logic cell; F1, clock, set and reset
inputs and the data input, I/O register clock,
reset and enable inputs as well as the output
enable control — each driven by an input-
only or I/O pin, or any logic cell output or
I/O cell feedback
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‡ Input + logic cell + output total delays
under 6 ns
‡ Data path speeds over 400 MHz
‡ Counter speeds over 300 MHz
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‡ Interfaces with both 3.3 V and 5.0 V devices
‡ PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
‡ Full JTAG boundary scan
‡ I/O Cells with individually controlled
Registered Input Path and Output Enables
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‡ 74 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
‡ Four High Drive input-only pins
‡ Four High Drive input-only/distributed
network pins
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Preliminary
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