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Datasheet QL3040-PDF.HTML Equivalent ( PDF ) |
N.º | Número de pieza | Descripción | Fabricantes | Category |
QL3 Datasheet ( Hoja de datos ) - resultados coincidentes |
N.º | Número de pieza | Descripción | Fabricantes | Catagory |
1 | QL3004 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3004 pASIC 3 FPGA Data Sheet
••••••
4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Device Highlights
High Performance & High Density
• 4,000 Usable PLD Gates with 74 I/Os • 300 MHz 16-bit
Eight Low-Skew Distributed Networks
• QuickLogic Corporation gate | | |
2 | QL3004E | PLD Gate pASIC 3 FPGA Combining High Performance and High Density 4/( S$6,& )3*$ 'DWD 6KHHW
8VDEOH 3/' *DWH S$6,& )3*$ &RPELQLQJ +LJK 3HUIRUPDQFH DQG +LJK 'HQVLW\
'HYLFH +LJKOLJKWV
+LJK 3HUIRUPDQFH
300 MHz 16-bit
+LJK 'HQVLW\
)RXU /RZ6NHZ 'LVWULEXWHG 1HWZRUNV
Two array clock/control networks available
4, QuickLogic Corporation gate | | |
3 | QL3006 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density 4/ S$6,& )3*$ 'DWD 6KHHW
8VDEOH 3/' *DWH S$6,& )3*$ &RPELQLQJ +LJK 3HUIRUPDQFH DQG +LJK 'HQVLW\
'HYLFH +LJKOLJKWV
+LJK 3HUIRUPDQFH
300 MHz 16-bit
+LJK 'HQVLW\
)RXU /RZ6NHZ 'LVWULEXWHG 1HWZRUNV
Two array clock/control networks available
6,0 QuickLogic Corporation gate | | |
4 | QL3012 | qASIC 3 FPGA . U 4 QL3012 pASIC 3 FPGA Data Sheet t e e h S ••••• • 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance a t a and High Density Eight Low-Skew Distributed Device .D Highlights w Networks w Two array clock/control networks available Performance & High Density wHigh to the log QuickLogic data | | |
5 | QL3025 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3025 pASIC 3 FPGA Data Sheet
••••••
25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Device Highlights
High Performance & High Density
• 25,000 Usable PLD Gates with 204 I/Os • 300 MHz 16-bit
Four Low-Skew Distributed Networks
� QuickLogic Corporation gate | | |
6 | QL3040 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3040 pASIC 3 FPGA Data Sheet
••••••
40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Device Highlights
High Performance & High Density
• 40,000 Usable PLD Gates with 252 I/Os • 300 MHz 16-bit
Eight Low-Skew Distributed Networks
� QuickLogic Corporation gate | | |
7 | QL3060 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3060 pASIC 3 FPGA Data Sheet
••••••
60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Device Highlights
High Performance & High Density
• 60,000 Usable PLD Gates with 316 I/Os • 300 MHz 16-bit
Eight Low-Skew Distributed Networks
� QuickLogic Corporation gate | |
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