PDF K7A161830B Data sheet ( Hoja de datos )

Número de pieza	K7A161830B
Descripción	512Kx36 & 1Mx18 Synchronous SRAM
Fabricantes	SAMSUNG ELECTRONICS
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No Preview Available ! K7A163630B K7A161830B 512Kx36 & 1Mx18 SynchronouwswwS.DRatAaShMeet4U.com 18Mb B-die Sync. SRAM Specification 100TQFP with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi- lar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. - 1 - July 2005 Rev 1.0 1 page K7A163630B K7A161830B PIN CONFIGURATION(TOP VIEW) 512Kx36 & 1Mx18 SynchronouwswwS.DRatAaShMeet4U.com NC/DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 NC/DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 Pin TQFP (20mm x 14mm) K7A163630B(512Kx36) 80 DQPb/NC 79 DQb7 78 DQb6 77 VDDQ 76 VSSQ 75 DQb5 74 DQb4 73 DQb3 72 DQb2 71 VSSQ 70 VDDQ 69 DQb1 68 DQb0 67 VSS 66 N.C. 65 VDD 64 ZZ 63 DQa7 62 DQa6 61 VDDQ 60 VSSQ 59 DQa5 58 DQa4 57 DQa3 56 DQa2 55 VSSQ 54 VDDQ 53 DQa1 52 DQa0 51 DQPa/NC PIN NAME SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO. A0 - A18 Address Inputs 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50,81,82,99,100 ADV Burst Address Advance 83 ADSP Address Status Processor 84 ADSC Address Status Controller 85 CLK Clock 89 CS1 Chip Select 98 CS2 Chip Select 97 CS2 Chip Select 92 WEx(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 GW Global Write Enable 88 BW Byte Write Enable 87 ZZ Power Down Input 64 LBO Burst Mode Control 31 VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd or N.C VDDQ VSSQ Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs Output Power Supply (3.3V or 2.5V) Output Ground 15,41,65,91 17,40,67,90 14,16,38,39,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. - 5 - July 2005 Rev 1.0 5 Page K7A163630B K7A161830B Output Load(A) Dout Zo=50Ω 512Kx36 & 1Mx18 SynchronouwswwS.DRatAaShMeet4U.com RL=50Ω VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O Dout 319Ω / 1667Ω 353Ω / 1538Ω 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIING CHARACTERISTICS Parameter Symbol -25 MIN MAX -16 Min Max Unit Cycle Time tCYC 4.0 - 6.0 - ns Clock Access Time tCD - 2.6 - 3.5 ns Output Enable to Data Valid tOE - 2.6 - 3.5 ns Clock High to Output Low-Z tLZC 0 - 0 - ns Output Hold from Clock High tOH 1.5 - 1.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 2.6 - 3.0 ns Clock High to Output High-Z tHZC 1.5 2.6 1.5 3.0 ns Clock High Pulse Width tCH 1.7 - 2.1 - ns Clock Low Pulse Width tCL 1.7 - 2.1 - ns Address Setup to Clock High tAS 1.2 - 1.5 - ns Address Status Setup to Clock High tSS 1.2 - 1.5 - ns Data Setup to Clock High tDS 1.2 - 1.5 - ns Write Setup to Clock High (GW, BW, WEX) tWS 1.2 - 1.5 - ns Address Advance Setup to Clock High tADVS 1.2 - 1.5 - ns Chip Select Setup to Clock High tCSS 1.2 - 1.5 - ns Address Hold from Clock High tAH 0.3 - 0.5 - ns Address Status Hold from Clock High tSH 0.3 - 0.5 - ns Data Hold from Clock High tDH 0.3 - 0.5 - ns Write Hold from Clock High (GW, BW, WEX) tWH 0.3 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.3 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.3 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - cycle Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. - 11 - July 2005 Rev 1.0 11 Page

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