PDF QL1P075 Data sheet ( Hoja de datos )

Número de pieza	QL1P075
Descripción	Ultra-Low Power FPGA Combining Performance
Fabricantes	QuickLogic
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QuickLogic PolarPro™ Data Sheet www.DataSheet4U.com • • • • • • Combining Low Power, Performance, Density, and Embedded RAM Device Highlights Flexible Programmable Logic • 0.18 µm, six layer metal CMOS process • 1.8 V core voltage, 1.8/2.5/3.3 V drive capable I/Os • Up to 202 kilobits of SRAM • Up to 292 I/Os available • Up to one million system gates • Nonvolatile, instant-on • IEEE 1149.1 boundary scan testing compliant Embedded Dual Port SRAM • Up to eight dual-port 4-kilobit high performance SRAM blocks • Embedded synchronous/asynchronous FIFO controller • Configurable and cascadable aspect ratio Programmable I/O • Bank programmable drive strength • Bank programmable slew rate control • Independent I/O banks capable of supporting multiple I/O standards in one device • Native support for DDR I/Os • Bank programmable I/O standards: LVTTL, LVCMOS, and LVCMOS18 • Quadrant-based segmentable clock networks 20 quad clock networks per device 4 quad clock networks per quadrant 1 dedicated clock network per quadrant • Two user Configurable Clock Managers (CCMs) Very Low Power (VLP) Mode • QuickLogic PolarPro has a special VLP pin which can enable a low power sleep mode that significantly reduces the overall power consumption of the device. • Enter VLP mode from normal operation in less than 250 µs • Exit from VLP mode to normal operation in less than 250 µs Security Links There are several security links to disable JTAG access to the device. Programming these optional links completely disables access to the device from the outside world and provides an extra level of design security not possible in SRAM-based FPGAs. Figure 1: QuickLogic PolarPro Block Diagram CCM DDR/GPIO DDR/GPIO DDR/GPIO Embedded RAM Blocks FIFO Controller DDR/GPIO CCM Fabric Advanced Clock Network • Multiple low skew clock networks 1 dedicated global clock network 4 programmable global clock networks GPIO FIFO Controller Embedded RAM Blocks GPIO GPIO GPIO © 2005 QuickLogic Corporation PRELIMINARY www.quicklogic.com •••••• 1 1 page QuickLogic PolarPro™ Data Sheet Rev. A www.DataSheet4U.com Figure 4: Horizontal and Vertical Concatenation Examples 256x36 Dual-Port RAM WD[35:0] WA[7:0] WEN[3:0] WD_SEL WCLK RA[7:0] RD_SEL RCLK RD[35:0] Horizontal Concatenation 512x18 Dual-Port RAM WD[17:0] WA[8:0] WEN[1:0] WD_SEL WCLK RA[8:0] RD_SEL RCLK RD[17:0] Vertical Concatenation Table 3 shows the various RAM configurations supported by the PolarPro RAM modules. Table 3: Available Dual-Port RAM Configurations Number of RAM Blocks 1 Depth 256 Width 1 to 18 1 512 1 to 9 2 256 1 to 36 2 512 1 to 18 2 1024 1 to 9 True Dual-Port RAM PolarPro dual-port RAM modules can also be concatenated to generate true dual-port RAMs. The true dual- port RAM module’s Port1 and Port2 have completely independent read and write ports, and separate read and write clocks. This allows Port1 and Port2 to have different data widths and clock domains. It is important to note that there is no circuitry preventing a write and read operation to the same address space at the same time. Therefore, it is up to the designer to ensure that the same address is not read from and written to simultaneously, otherwise the data is considered invalid. Likewise, the same address must not be written to from both ports at the same time. However, it is possible to read from the same address. Figure 5 shows an example of a 512x18 true dual-port RAM. © 2005 QuickLogic Corporation PRELIMINARY www.quicklogic.com •••••• 5 5 Page Distributed Clock Networks QuickLogic PolarPro™ Data Sheet Rev. A www.DataSheet4U.com Global Clocks The PolarPro clock network architecture consists of a 2-level H-tree network as shown in Figure 9. The first level of each clock tree (high-lighted in red) spans from the clock input pad to the global clock network and to the center of each quadrant of the chip. The second level (high-lighted in blue) spans from the quadrant clock network to every logic cell inside that quadrant. There are five global clocks in the global clock network, and five quadrant clocks in each quadrant clock network. All global clocks drive the quadrant clock network inputs. The quadrant clocks output to clock inversion muxes, which pass either the original input clock or an inverted version of the input clock to the logic cells in that quadrant. The clock networks can drive RAM block clock inputs and reset, set, enable, and clock inputs to I/O registers. Furthermore, the quadrant clock outputs can be routed to all logic cell inputs. Figure 9: Global Clock Architecture Quadrant Clock x4 Network Inversion Mux Quadrant Clock x4 Network Global Clock Network x4 x4 Quadrant Clock Network x4 Quadrant Clock Network Of the five global clock networks, four can be either driven directly by clock pads, Configurable Clock Manager (CCM) outputs, or internally generated signals. These four clock nets go through 3-input global clock muxes located in the middle of the die. See Figure 10 for a diagram of a 3-input global clock mux. The fifth is a dedicated global clock network that goes directly to the quadrant quad-net clock network and is used as a dedicated fast clock. © 2005 QuickLogic Corporation PRELIMINARY www.quicklogic.com •••••• 11 11 Page

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