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QL1P600 fiches techniques PDF

QuickLogic - Ultra-Low Power FPGA Combining Performance

Numéro de référence QL1P600
Description Ultra-Low Power FPGA Combining Performance
Fabricant QuickLogic 
Logo QuickLogic 





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QL1P600 fiche technique
QuickLogic PolarPro™ Data Sheet
www.DataSheet4U.com
• • • • • • Combining Low Power, Performance, Density, and Embedded RAM
Device Highlights
Flexible Programmable Logic
• 0.18 µm, six layer metal CMOS process
• 1.8 V core voltage, 1.8/2.5/3.3 V drive
capable I/Os
• Up to 202 kilobits of SRAM
• Up to 292 I/Os available
• Up to one million system gates
• Nonvolatile, instant-on
• IEEE 1149.1 boundary scan testing compliant
Embedded Dual Port SRAM
• Up to eight dual-port 4-kilobit high performance
SRAM blocks
• Embedded synchronous/asynchronous FIFO
controller
• Configurable and cascadable aspect ratio
Programmable I/O
• Bank programmable drive strength
• Bank programmable slew rate control
• Independent I/O banks capable of supporting
multiple I/O standards in one device
• Native support for DDR I/Os
• Bank programmable I/O standards: LVTTL,
LVCMOS, and LVCMOS18
• Quadrant-based segmentable clock networks
 20 quad clock networks per device
 4 quad clock networks per quadrant
 1 dedicated clock network per quadrant
• Two user Configurable Clock Managers (CCMs)
Very Low Power (VLP) Mode
• QuickLogic PolarPro has a special VLP pin which
can enable a low power sleep mode that
significantly reduces the overall power
consumption of the device.
• Enter VLP mode from normal operation in less
than 250 µs
• Exit from VLP mode to normal operation in less
than 250 µs
Security Links
There are several security links to disable JTAG
access to the device. Programming these optional
links completely disables access to the device from
the outside world and provides an extra level of
design security not possible in SRAM-based FPGAs.
Figure 1: QuickLogic PolarPro Block Diagram
CCM DDR/GPIO
DDR/GPIO
DDR/GPIO
Embedded RAM Blocks
FIFO Controller
DDR/GPIO CCM
Fabric
Advanced Clock Network
• Multiple low skew clock networks
 1 dedicated global clock network
 4 programmable global clock networks
GPIO
FIFO Controller
Embedded RAM Blocks
GPIO
GPIO
GPIO
© 2005 QuickLogic Corporation
PRELIMINARY
www.quicklogic.com ••••••
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