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PDF LQ035Q7DB02R Data sheet ( Hoja de datos )
| Número de pieza | LQ035Q7DB02R | |
| Descripción | TFT-LCD Module | |
| Fabricantes | SHARP Electronic | |
| Logotipo |  |
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PRODUCT SPECIFICATIONS
www.DataSheet4U.com
Mobile Liquid Crystal Displays Group
LQ035Q7DB02R
TFT-LCD Module
Spec. Issue Date: June 16, 2005
No: LCP-05011
1 page  
(1) Application
This specification applies to LQ035Q7DB02R.
www.DataSheet4U.com
(2) Overview
This module is a color reflective and active matrix LCD module incorporating amorphous silicon TFT
(Thin Film Transistor), named AD-TFT(Advanced TFT). It is composed of a color TFT-LCD panel, driver
ICs, an FPC, a back light, a touch panel and a back sealed casing. It isn’t composed control circuit.
Graphics and texts can be displayed on a 240 3 320 dots panel with 262,144 colors by supplying.
Optimum view angle is 6 o’clock. An inverted display mode is selective in the vertical or the horizontal
direction.
3 Mechanical specifications
Table 1
Parameter
Specifications
Units
Remarks
Screen size (Diagonal)
8.9 [3.52 ] Diagonal
cm
Display active area
53.64 H 71.52 V
mm
Pixel format
240(H) 320(V)
pixels
(1 pixel = R+G+B dots)
Pixel pitch
0.2235 H 0.2235 V
mm
Pixel configuration
R,G,B vertical stripe
Unit outline dimension
65.0(W) 85.0(H) 4.5 (D)
mm Note3-1
Mass
50 TYP.
Surface hardness
3H
Note 3-1
Excluding protrusion. For detailed measurements and tolerances, please refer to Fig. 1.
(4)Pixel configuration
(1,1)
RGB
(240,1)
Display area
(1,320)
FPC
(240,320)
5 Page 
7-2) Timing Characteristics of input signals
Table 8 AC Characteristics (1)
(VSHA=+5V, VSHD=+w3w.3wV.,DTaata=S2h5eet4)U.com
Parameter
Symbol Min. Typ.
Max.
Unit
Remark
Clock frequency of source driver
fCK 4.5
6.8 MHz
Rising time of clock
Tcr
20 ns
Falling time of clock
Tcf
20 ns DCLK
Pulse width (High level)
Tcwh
40
ns
Pulse width (Low level)
Tcwl
40
ns
Frequency of start pulse
fsp 16.5
28 kHz
Setup time of start pulse
Tsusp
15
ns SPL,SPR
Source
driver
Hold time of start pulse
Pulse width of start pulse
Setup time of latch pulse
Thsp
Twsp
Tsulp
10
20
ns
1.5/fCK ns Note 7-7
ns
Hold time of latch pulse
Thlp
20
ns LP
Pulse width of latch pulse Twlp
60
ns
Setup time of PS
Tsups
0
s
Setup time of PS
Hold time of PS
Tsulps
Thps
1
0
s
s PS
Hold time of PS
Thlps
30
ns
Set up time of data
Tsud
15
ns R0 R5,G0 G5
Hold time of data
Thd 10
ns ,B0 B5
Clock frequency
fcls 16.5
28 kHz
Pulse width of clock(Low)
Twlcls
5
(1/fcls)-30
s
Pulse width of clock(High) Twhcls 30
s
Rising time of clock
Trcls
100 ns CLS
Falling time of clock
Tfcls
100 ns
Gate Setup time of clock
Tsucls
3
s
driver Hold time of clock
Thcls
0
s
Frequency of start pulse
fsps 58
86 Hz
Setup time of start pulse
Tsusps 100
ns
Hold time of start pulse
Thsps 300
ns SPS
Rising time of start pulse
Trsps
100 ns
Falling time of start pulse
Tfsps
100 ns
Vcom Setup time of Vcom
Tsuvcom 0
s Vcom
Hold time of Vcom
Thvcom 1
s
Note 7-7 There must be only one up-edge of DCLK (includes Tsusp and Thsp time) in the period of
SPL=”Hi”.
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