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PDF ADF5002 Data sheet ( Hoja de datos )
| Número de pieza | ADF5002 | |
| Descripción | 4GHz to 18GHz Divide-by-8 Prescaler | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Divide-by-8 prescaler
High frequency operation: 4 GHz to 18 GHz
Integrated RF decoupling capacitors
Low power consumption
Active mode: 30 mA
Power-down mode: 7 mA
Low phase noise: −153 dBc/Hz
Single dc supply: 3.3 V compatible with ADF4xxx PLLs
Temperature range: −40°C to +105°C
Small package: 3 mm × 3 mm LFCSP
APPLICATIONS
PLL frequency range extender
Point-to-point radios
VSAT radios
Communications test equipment
GENERAL DESCRIPTION
The ADF5002 prescaler is a low noise, low power, fixed RF
divider block that can be used to divide down frequencies as
high as 18 GHz to a lower frequency suitable for input to a
PLL IC, such as the ADF4156 or the ADF4106. The ADF5002
provides a divide-by-8 function. The ADF5002 operates from
a 3.3 V supply and has differential 100 Ω RF outputs to allow
direct interface to the differential RF inputs of PLLs such as
the ADF4156 and ADF4106.
4 GHz to 18 GHzwww.DataSheet4U.com
Divide-by-8 Prescaler
ADF5002
FUNCTIONAL BLOCK DIAGRAM
CE
RFIN
3pF
50Ω
BIAS
DIVIDE
BY 8
ADF5002
VDDx
100Ω
100Ω
1pF
1pF
RFOUT
RFOUT
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF5002www.DataSheet4U.com
GND 1
RFIN 2
GND 3
GND 4
PIN 1
INDICATOR
ADF5002
TOP VIEW
(Not to Scale)
12 GND
11 RFOUT
10 RFOUT
9 GND
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE MUST BE
CONNECTED TO GND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 3, 4, 5, 8, 9, GND
12, 13, 16
RF Ground. All ground pins should be tied together.
2 RFIN Single-Ended 50 Ω Input to the RF Prescaler. This pin is ac-coupled internally via a 3 pF capacitor.
6 NC No Connect. This pin can be left unconnected.
7 CE Chip Enable. This pin is active high. When CE is brought low, the part enters power-down mode. If this
functionality is not required, the pin can be left unconnected because it is pulled up internally through
a weak pull-up resistor.
10
RFOUT
Divided-Down Output of the Prescaler. This pin has an internal 100 Ω load resistor tied to VDD2 and an
ac-coupling capacitor of 1 pF.
11
RFOUT
Complementary Divided-Down Output of the Prescaler. This pin has an internal 100 Ω load resistor tied
to VDD2 and an ac-coupling capacitor of 1 pF.
14
VDD2
Voltage Supply for the Output Stage. This pin should be decoupled to ground with a 0.1 μF capacitor in
parallel with a 10 pF capacitor and can be tied directly to VDD1.
15
VDD1
Voltage Supply for the Input Stage and Divider Block. This pin should be decoupled to ground with a
0.1 μF capacitor in parallel with a 10 pF capacitor.
EPAD
The LFCSP has an exposed paddle that must be connected to GND.
Rev. 0 | Page 5 of 12
5 Page 
NOTES
ADF5002www.DataSheet4U.com
Rev. 0 | Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADF5002.PDF ] | |
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