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PDF LI0201 Data sheet ( Hoja de datos )
| Número de pieza | LI0201 | |
| Descripción | Ferrite Chip Beads | |
| Fabricantes | Laird Technologes | |
| Logotipo |  |
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Innovative Technology
for a Connected World
LI0201www.DataSheet4U.com
Ferrite Chip Beads
Laird Technologies has broadened its Ferrite Chip Bead product offering by adding the smaller EIA 0201
(Metric 0603) version to the existing EIA 0402 ~ 3312 (Metric 1005 ~ 8531) product family. The smaller
foot-print makes this chip bead ideal for miniature and portable electronic system devices. The new LI0201
series is an ultra-compact, monolithic EMI suppression chip designed for digital signal lines. It offers space
efficiency with superior EMI noise filtering over a wide frequency range of low to several hundred MHz for
broad-band signal interfaces, up to GHz ranges for high-frequency signal lines.
FEATURES
• Rugged monolithic construction
• Smaller foot-print: 0.6 mm x 0.3 mm x 0.3 mm
• Superior impedance vs. frequency characteristics with
low DCR
• EMI noise suppression for high frequency and
broad-band signal lines
• Lead free and RoHS compliant
MARKETS
• Advanced hand-held devices
• Cellular phones
• Bluetooth headsets
• PDAs
• GPS
• MP3 players
• Digital camcorders and cameras
ELECTRICAL PROPERTIES
Part Number
LI0201C330R-10
LI0201C560R-10
LI0201B800R-10
LI0201C800R-10
LI0201E800R-10
LI0201B121R-10
LI0201C121R-10
LI0201B241R-10
Metric
Package
Size
0603
0603
0603
0603
0603
0603
0603
0603
Impedance (Ω)
25 100 500
1
MHz MHz MHz GHz
7 33 113 153
11 56 186 252
31 80 195 224
18 80 335 428
41 80 119 116
39 120 247 269
59 120 189 182
81 240 586 321
Peak Impedance
Frequency
(MHz)
Impedance
(Ω)
1646
1347
978
903
605
800
630
390
171
268
225
434
120
275
190
619
DCR
Max
(Ω)
0.5
0.6
0.8
0.6
0.5
0.8
0.7
1
Current Rating
(mA)
300
300
200
300
500
200
300
200
MECHANICAL DIMENSIONS
Land Pattern
global solutions: local support TM
USA: +1 800 634.2673
+1 423 308.1690
Europe: +49 8031.2460.0
Asia: +86 755.2714.1166
www.lairdtech.com
Metric
(EIA)
Pkg
Size
0603
(0201)
A
mm
(inch)
0.60
(.024)
B
mm
(inch)
0.30
(.012)
C
mm
(inch)
0.30
(.012)
D
mm
(inch)
0.15
(.006)
G
mm
(inch)
H
mm
(inch)
L
mm
(inch)
0.25 0.32 0.69
(.010) (.013) (.027)
1 page  
Innovative Technology
for a Connected World
LI0201www.DataSheet4U.com
Ferrite Chip Beads
Application Notes
LEAD-FREE/ROHS COMPLIANCE
All Laird Technologies’ surface mount and through hole EMI components (including assemblies with wire and cofired monolithic ferrite
chip beads and common mode chokes) are available lead-free and RoHS compliant.
PART NUMBERING SYSTEM
Lead-free board level part numbers are differentiated by a suffix descriptor. The suffix (-10) identifies the part number for all lead-free
parts. This part number suffix is for use on board level part numbers only.
PART NUMBER EXAMPLES
Old Part HZ0805E601R-00 contains lead
New Part HZ0805E601R-10 is lead-free
Old Part 28F0121-0SR contains lead
New Part 28F0121-0SR-10 is lead-free
All Laird Technologies’ new and old ferrite cable cores are RoHS compliant. No part number change for cable cores.
COMPOSITION
Laird Technologies’ lead-free component terminations and wire platings are 100% matte Tin (Sn) over a Nickel (Ni) barrier and are
reverse compatible with existing Tin (Sn)/Lead (Pb) materials.
Concerns over the use of pure tin coatings on component leads and terminations, due to the possibility of tin whiskering, are still under
industry discussion. Electroplating 100% matte tin over a nickel barrier is recognized as an effective whisker growth mitigation strategy
that is accepted by most industry groups. Laird Technologies’ maintains a minimum plating thickness of 2.5µm [99µin] of Tin, and
0.7µm [28µin] of Nickel.
RECOMMENDED LEAD-FREE
SOLDERING PROFILE
While Laird Technologies’ lead-free surface mount and
through hole components are reverse compatible with
existing Sn/Pb materials, higher peak temperatures (up to
260°C) provide better wetting characteristics during the
solder reflow process. The higher reflow temperatures
typically used for lead-free processes will not damage
Laird Technologies’ surface mount components, but
the delta T between the board and larger components
must be considered. Smaller delta Ts can be achieved
with slower belt speed to increase the pre-heat time.
Soldering cycle time (throughput) must be balanced with
reflow temperature. Allowance must be made for the
coldest part (largest heat sink) to solder, considering the
thermal mass of the board and size of the components.
global solutions: local support TM
USA: +1 800 634.2673
+1 423 308.1690
Europe: +49 8031.2460.0
Asia: +86 755.2714.1166
www.lairdtech.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet LI0201.PDF ] | |
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