AT49BV8011T Datasheet PDF - ATMEL Corporation
| Part Number | AT49BV8011T | |
| Description | 8-megabit (512K x 16/1M x 8) 3-volt Only Flash Memory | |
| Manufacturers | ATMEL Corporation | |
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Features
• Single Supply for Read and Write: 2.7V to 3.3V (BV), 3.0V to 3.3V (LV)
• Access Time – 90 ns
• Sector Erase Architecture
Fourteen 32K Word (64K Byte) Sectors with Individual Write Lockout
Two 16K Word (32K Byte) Sectors with Individual Write Lockout
Two 8K Word (16K Byte) Sectors with Individual Write Lockout
Four 4K Word (8K Byte) Sectors with Individual Write Lockout
• Fast Word Program Time – 20 µs
• Fast Sector Erase Time – 200 ms
• Dual Plane Organization, Permitting Concurrent Read while Program/Erase
Memory Plane A: Four 4K Word, Two 8K Word and Two 16K Word Sectors
Memory Plane B: Fourteen 32K Word Sectors
• Erase Suspend Capability
– Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
• Low-power Operation
– 25 mA Active
– 10 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• Optional VPP Pin for Fast Programming
• RESET Input for Device Initialization
• Sector Program Unlock Command
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
Description
The AT49BV/LV8011(T) is a 2.7- to 3.3-volt 8-megabit Flash memory organized as
524,288 words of 16 bits each or 1,048,576 bytes of 8 bits each. The x16 data
appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided
into 22 sectors for erase operations. The device is offered in 48-pin TSOP and 48-ball
CBGA packages. The device has CE, and OE control signals to avoid any bus
Pin Configurations
(continued)
Pin Name
A0 - A18
CE
OE
WE
RESET
RDY/BUSY
VPP
I/O0 - I/O14
I/O15 (A-1)
BYTE
NC
VCCQ
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
READY/BUSY Output
Optional Power Supply for Faster
Program/Erase Operations
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
Output Power Supply
8-megabit
(512K x 16/1M x 8)
3-volt Only
Flash Memory
AT49BV8011
AT49BV8011T
AT49LV8011
AT49LV8011T
Rev. 1265E–01/00
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AT49BV/LV8011(T)
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For details, see “Operating Modes” (for hardware opera-
tion) or “Software Product Identification”. The manufacturer
and device code is the same for both modes.
DATA POLLING: The AT49BV/LV8011(T) features DATA
polling to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte/word loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle. Please see “Status Bit Table” for more details.
TOGGLE BIT: In addition to DATA polling, the
AT49BV/LV8011(T) provides another method for determin-
ing the end of a program or erase cycle. During a program
or erase operation, successive attempts to read data from
the same memory plane will result in I/O6 toggling between
“1” and “0”. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2, which can be
used in conjunction with the toggle bit that is available on
I/O6. While a sector is erase suspended, a read or a
program operation from the suspended sector will result in
the I/O2 bit toggling. Please see “Status Bit Table” for more
details.
RDY/BUSY: An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR-tying of several devices to the same
RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49BV/LV8011(T) in the following ways: (a) VCC sense: if
VCC is below 1.8V (typical), the program function is inhib-
ited. (b) VCC power on delay: once VCC has reached the
VCC sense level, the device will automatically time out
10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS: While operating with a 2.7V to 3.3V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
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| Information | Total 18 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ AT49BV8011T.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| AT49BV8011 | The function is 8-megabit (512K x 16/1M x 8) 3-volt Only Flash Memory. ATMEL Corporation | |
| AT49BV8011T | The function is 8-megabit (512K x 16/1M x 8) 3-volt Only Flash Memory. ATMEL Corporation | |
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