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PDF 73M1903 Data sheet ( Hoja de datos )
| Número de pieza | 73M1903 | |
| Descripción | Modem Analog Front End | |
| Fabricantes | TDK Semiconductor | |
| Logotipo |  |
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DESCRIPTION
The TDK 73M1903 Analog Front End (AFE) IC
includes fully differential hybrid driver outputs,
which connect to the telephone line interface
through a transformer-based DAA. The receive
pins are also fully differential for maximum
flexibility and performance. This arrangement
allows for the design of a high performance
hybrid circuit to improve signal to noise
performance under low receive level conditions,
and compatibility with any standard transformer
intended for PSTN communications applications.
The device incorporates a programmable
sample rate circuit to support soft modem and
DSP based implementations of all speeds up to
V.92 (56Kbps). The sampling rates supported
are from 7.2kHz to 14.4kHz by programming
pre-scaler NCO and PLL NCO.
The TDK 73M1903 device incorporates a digital
host interface that is compatible with the serial
ports found on most commercially available
DSPs and processors and exchanges both
payload and control information with the host.
Cost saving features of the device include an
input reference frequency circuit, which accepts
a range of crystals from 9-27MHz. It also
accepts external reference clock values between
9-40MHz generated by the host processor. In
most applications, this eliminates the need for a
dedicated crystal oscillator and reduces the bill
of material (BOM).
The 73M1903 also supports two analog loop
back and one digital loop back test modes.
The 73M1903 in 32-TQFP package is footprint
compatible with 73M2901CL embedded modem
and allows for the same circuit design to
accommodate soft modem, V.22bis hard
modem, and high speed (V.32bis/V.34/V.92)
applications through population of an external
data pump device.
73M1903
Modem Analog Front End
PRODUCT DATA SHEET
JANUARY 2004
FEATURES
• Up to 56Kbps (V.92) performance
• Programmable sample rates (7.2 - 14.4kHz)
• Reference clock range of 9-40MHz
• Crystal frequency range of 9-27MHZ
• Host synchronous serial interface operation
• Pin compatible with 73M2901CL modem
• Low power modes
• On board line interface drivers
• Fully differential receiver and transmitter
Drivers for transformer interface
• 3.0V – 3.6V operation
• 5V tolerant I/O
• Industrial temperature range (-40 to +85°C)
• JATE compliant transmit spectrum
• Package options: 32-TQFP and 32-MLF
APPLICATIONS
• Set Top Boxes
• Personal Video Recorders (PVR)
• Multifunction Peripherals (MFP)
• Fax Machines
• Internet Appliances
• Game Consoles
• Point of Sale Terminals
• Automatic Teller Machines
• Speaker Phones
• RF Modems
TXAP
TXAN
(HYBRID)
Transmit
Drivers/
Filters
Analog
Sigma
Delta
VBG
Ref.
RXAP
RXAN
Receive
Mux/
Filters
Control Serial
DAC Registers Port
GPIO
HOOK
DAA
Controls Clocks
Control
Logic
Crystal
SCLK
SDIN
SDOUT
FSB
http://www.tdksemiconductor.com TDK SEMICONDUCTOR CONFIDENTIAL
1/08/04 R4.031
1 page  
73M1903
Modem Analog Front End
PRODUCT DATA SHEET
SIGNAL DESCRIPTION
The TDK 73M1903 modem AFE IC is available in a 32 pin TQFP or MLF package with same pin out. The
following table describes the function of each pin. There are two pairs of power supply pins, VPA(analog)
and VPD(digital). They should be separately decoupled from the supply source in order to isolate digital
noise from the analog circuits internal to the chip. Failure to adequately isolate and decouple these
supplies will compromise device performance.
PIN NAME TYPE PIN #
DESCRIPTION
VND
VNA
VPD
VPA
VPPLL
VNPLL
RST
OSCIN
OSCOUT
GPIO(0-7)
VREF
RXAP
RXAN
TXAP
TXAN
SCLK
SDOUT
SDIN
FS
TYPE
SckMode
GND
GND
PWR
PWR
PWR
PWR
I
I
O
I/O
O
I
I
O
O
O
O
I
O
I
I
1,22
16
2,25
10
20
17
9
19
18
3, 4, 5, 6,
23, 24,30,31
13
15
14
12
11
8
32
29
Negative Digital Ground
Negative Analog Ground
Positive Digital Supply
Positive Analog Supply
Positive PLL Supply, shared with VPD
Negative PLL Ground
Master reset. When this pin is a logic 0 all registers are reset to
their default states; Weak-pulled high- default
Crystal oscillator input. When providing an external clock
source, drive OSCIN.
Crystal oscillator circuit output pin.
Software definable digital input/output pins.
Reference voltage pin (Reflects Vref)
Receive analog positive input.
Receive analog negative input.
Transmit analog positive output
Transmit analog negative output
Serial interface clock. With SCLK continuous selected,
Frequency = 256*Fs ( =2.4576MHz for Fs=9.6kHz)
Serial data output (or input to the host).
Serial data input (or output from the host)
7 Frame synchronization. (Active Low)
27
Type of frame sync. Open, weak-pulled high = early (mode1);
tied low = late (mode0)
28
Controls the SCLK behavior after FS. Open, weak-pulled high
= SCLK Continuous; tied low = 32 clocks per R/W cycle.
Table 1: -32 TQFP and MLF Pin Description
http://www.tdksemiconductor.com TDK SEMICONDUCTOR CONFIDENTIAL
5 / 46
1/08/04 R4.031
5 Page 
73M1903
Modem Analog Front End
PRODUCT DATA SHEET
SCLK
FS(mode1)
SDIN
SDOUT
SCLK
FS(mode1)
SDIN
SDOUT
SCLK
FS(mode0)
SDIN
SDOUT
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 CTL
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
Data Frame With Early Frame Sync
R/W A6 A5 A4 A3 A2 A1 A0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
zero
zero
zero
zero
zero
zero zero zero DO7 DO6 DO5
Control Frame With Early Frame Sync
DO4
DO3
DO2
DO1
DO0
R/W A6 A5 A4 A3 A2 A1 A0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
zero
zero
zero
zero
zero
zero zero zero DO7 DO6 DO5
Control Frame With Late Frame Sync
DO4
DO3
DO2
DO1
DO0
SCLK
FS
SDIN
SDOUT
7.2KHz (8KHz)
TX TX TX
RX RX RX
Data Frame
TX TX 1
RX RX RX
R A AA
DI DI DI
0 0 00
DO DO DO
Control Frame
Relation Between the Data and Control Frames
TX TX TX
TX TX 0
RX RX RX
RX RX RX
Data Frame
Figure 3 -Serial Port Timing Diagram
http://www.tdksemiconductor.com TDK SEMICONDUCTOR CONFIDENTIAL
11 / 46
1/08/04 R4.031
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 73M1903.PDF ] | |
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