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PDF AT49BV802D Data sheet ( Hoja de datos )
| Número de pieza | AT49BV802D | |
| Descripción | 8-megabit (512K x 16/ 1M x 8) 3-volt Only Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single Voltage Read/Write Operation: 2.65V to 3.6V
• Access Time – 70 ns
• Sector Erase Architecture
– Fifteen 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
• Fast Byte/Word Program Time – 10 µs
• Fast Sector Erase Time – 100 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Byte/Word in the Non-suspending Sectors by Suspending
Programming of Any Other Byte/Word
• Low-power Operation
– 10 mA Active
– 15 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• RESET Input for Device Initialization
• Sector Lockdown Support
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Minimum 100,000 Erase Cycles
• Common Flash Interface (CFI)
• Green (Pb/Halide-free) Packaging
8-megabit
(512K x 16/
1M x 8)
3-volt Only
Flash Memory
AT49BV802D
AT49BV802DT
1. Description
The AT49BV802D(T) is a 2.7-volt 8-megabit Flash memory organized as 524,288
words of 16 bits each or 1,048,576 bytes of 8 bits each. The x16 data appears on
I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 23 sec-
tors for erase operations. The AT49BV802D(T) is offered in a 48-lead TSOP and a
48-ball CBGA package. The device has CE and OE control signals to avoid any bus
contention. This device can be read or reprogrammed using a single power supply,
making it ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place the
device in other operation modes such as program and erase. The device has the
capability to protect the data in any sector (see “Sector Lockdown” section).
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors
within the memory. The end of a program or an erase cycle is detected by the
READY/BUSY pin, Data Polling or by the toggle bit.
3626A–FLASH–2/07
1 page  
AT49BV802D(T)www.DataSheet4U.com
4.3 Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET input halts the
present device operation and puts the outputs of the device in a high impedance state. When a
high level is reasserted on the RESET pin, the device returns to the read or standby mode,
depending upon the state of the control inputs.
4.4 Erasure
Before a byte/word can be reprogrammed, it must be erased. The erased state of memory bits is
a logical “1”. The entire device can be erased by using the Chip Erase command or individual
sectors can be erased by using the Sector Erase command.
4.4.1
Chip Erase
The entire device can be erased at one time by using the six-byte chip erase software code.
After the chip erase has been initiated, the device will internally time the erase operation so that
no external clocks are required. The maximum time to erase the chip is tEC.
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that
has been locked out; it will erase only the unprotected sectors. After the chip erase, the device
will return to the read or standby mode.
4.4.2
Sector Erase
As an alternative to a full chip erase, the device is organized into 23 sectors (SA0 - SA22) that
can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector
address is latched on the falling WE edge of the sixth cycle while the 30H data input command is
latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth
cycle. The erase operation is internally controlled; it will automatically time to completion. The
maximum time to erase a sector is tSEC. When the sector programming lockdown feature is not
enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a
sector that has been protected will result in the operation terminating immediately.
4.5 Byte/Word Programming
Once a memory block is erased, it is programmed (to a logical “0”) on a byte-by-byte or on a
word-by-word basis. Programming is accomplished via the internal device command register
and is a four-bus cycle operation. The device will automatically generate the required internal
program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If a
hardware reset happens during programming, the data at the location being programmed will be
corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase opera-
tions can convert “0”s to “1”s. Programming is completed after the specified tBP cycle time. The
Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program
cycle. If the erase/program status bit is a “1”, the device was not able to verify that the erase or
program operation was performed successfully.
3626A–FLASH–2/07
5
5 Page 
Figure 4-3. Toggle Bit Algorithm
(Configuration Register = 00)
START
Read I/O7 - I/O0
Read I/O7 - I/O0
AT49BV802D(T)www.DataSheet4U.com
Figure 4-4. Toggle Bit Algorithm
(Configuration Register = 01)
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
Toggle?
YES
NO I/O5 = 1?
NO
YES
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
YES
NO I/O5 = 1?
NO
YES
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
NO
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful,
Device in
Read Mode
Toggle Bit =
Toggle?
NO
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
3626A–FLASH–2/07
11
11 Page | ||
| Páginas | Total 31 Páginas | |
| PDF Descargar | [ Datasheet AT49BV802D.PDF ] | |
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