CL-GD6215 Datasheet PDF - Cirrus Logic
| Part Number | CL-GD6215 | |
| Description | Single DRAM LCD/VGA Controllers | |
| Manufacturers | Cirrus Logic | |
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CL-GD62XXwww.DataSheet4U.com
® Preliminary Data Book
FEATURES
s IBM®_VGA hardware-compatible
s Integrated RAMDAC™
s Integrated programmable frequency synthesizer
— 65 MHz at 5.0V; 40 MHz at 3.3V
s Supports single 256K x 16 DRAM configuration
— Symmetric or asymmetric RAS/CAS-address DRAM
s Color STN panel support (CL-GD6225/’6235 only)
— Dual-scan color STN panel support (CL-GD6235 only)
— 8- and 16-bit interfaces (no extra components required)
— Up to 256 simultaneous colors from a palette of 256K
s Integrates color TFT panel support
— Supports 9-, 12-, 15-, and 18-bit TFT panels
— Up to 256 simultaneous colors from a palette of 256K
s Connects directly to local bus, ISA bus (PC AT) or PI
bus (CL-GD6205 connects to ISA bus only)
s Windows performance-improvement features
— True packed-pixel addressing
— Improved data latches for block moves
— Color expansion for 8 bits-per-pixel graphics
— 32 x 32 hardware cursor (2 bits-per-pixel)
s Supports 3.3V and 5.0V mixed-voltage operation
s Standby and Suspend modes save power
— Internal timers for backlight control and Standby mode
— Dedicated Hardware-suspend Mode pin
— 32-kHz DRAM refresh clock in Suspend mode
s Frame-Accelerator for low-active power
— No additional DRAMs required
— Supports self-refresh DRAMs
s Simultaneous CRT and LCD (SimulSCAN™) operation
(cont.)
Single DRAM LCD/VGA
Controllers for Monochrome/
Color Notebook Computers
OVERVIEW
The CL-GD62XX (CL-GD6205/’6215/’6225/’6235) fam-
ily of advanced single-chip flat panel VGA controllers are
designed for use in portable systems with stringent
power consumption and form-factor requirements.
Product family pin compatibility provides easy upgrade
capability to color or higher-performance systems.
Integration of the frequency synthesizer, RAMDAC,
monochrome and color STN/TFT panel interfaces mini-
mizes the form-factor requirement for color and mono-
chrome graphics subsystems. All necessary panel-
power sequencing logic has been integrated into the
CL-GD62XX family, and a complete graphics subsystem
can be built using only two active components (in less
than three square inches).
The CL-GD62XX family uses a single 256K x 16 DRAM
(or four 256K x 4 DRAMs) for video memory. For added
flexibility, dual-CAS*-DRAM and dual-WE*-DRAM con-
figurations are supported.
With integrated Frame-Accelerator technology, the
CL-GD62XX controllers feature low-power LCD opera-
tion, yet support high LCD panel vertical-refresh rates.
No additional DRAMs are required for frame
(cont.)
Functional
Block Diagram
3.3V
3.3V or 5V
256K x 16
DRAM
3.3V or 5V
CL-GD62XX
160-Pin PQFP
3.3V
or
5V
3.3V
or
5V
5
4
3
2
1
0
ANALOG CRT
5
4
3
2
1
0
REFERENCE FREQUENCY
MONOCHROME OR
COLOR LCD PANEL
October 1993
Thi d
d ihF M k 404
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CL-GD62XX
LCD VGA Controller Family
www.DataSheet4U.com
List of Figures
Figure 2–1.
Figure 2–2.
Figure 7–1.
Figure 7–2.
Figure 7–3.
Figure 7–4.
Figure 7–5.
Figure 7–6.
Figure 7–7.
Figure 7–8.
Figure 7–9.
Typical Memory Clock Filter . . . . . . . . 35
Typical Video Clock Filter . . . . . . . . . . 35
Bus Signal Timing (ISA Bus) . . . . . . . 131
BALE Timing (ISA Bus) . . . . . . . . . . . 132
EROM* Timing (ISA Bus) . . . . . . . . . 133
AEN Timing (ISA Bus). . . . . . . . . . . . 133
PI Bus Interface Timing. . . . . . . . . . . 135
CLK1X, CLK2X Timing
(Local Bus) . . . . . . . . . . . . . . . . . . . . 136
Reset Timing (Local Bus) . . . . . . . . . 137
ADS#, LBA# Timing (Local Bus)
(Not Pipelined) . . . . . . . . . . . . . . . . . 138
LBA#, BS16# Timing (Local Bus)
(Pipelined). . . . . . . . . . . . . . . . . . . . . 139
Figure 7–10. BRDY# Delay (Local Bus). . . . . . . . .140
Figure 7–11. Read Data Timing (Local Bus) . . . . .140
Figure 7–12. Buffer Control Timing: 16-Bit Cycle
(’486 Local Bus) . . . . . . . . . . . . . . . .141
Figure 7–13. Display-Memory Bus Read Timing
(t = MCLK) . . . . . . . . . . . . . . . . . . . .143
Figure 7–14. Display-Memory Bus Write Timing . .145
Figure 7–15. CAS*-Before-RAS* Refresh Timing
(Display Memory Bus). . . . . . . . . . . .146
Figure 7–16. Reset Timing . . . . . . . . . . . . . . . . . . .147
Figure 7–17. STN Monochrome and Color-Passive
LCD Interface Timing . . . . . . . . . . . .149
Figure 7–18. TFT, EL , Plasma Color, and
Monochrome Single-Scan LCD Interface
Timing . . . . . . . . . . . . . . . . . . . . . . . .151
List of Tables
Table 1–1.
Table 1–2.
Table 1–3.
Table 1–4.
Table 1–5.
Table 1–6.
Table 1–7.
Table 1–8.
Table 4–1.
Table 4–2.
Table 4–3.
Table 4–4.
Table 5–1.
Table 6–1.
Table 6–2.
Table 6–3.
Table 7–0.
Table 7–1.
Table 7–2.
Table 7–3.
Host Interface . . . . . . . . . . . . . . . . . . . 19
CRT Interface . . . . . . . . . . . . . . . . . . . 20
LCD Flat Panel Interface. . . . . . . . . . . 20
Display Memory Interface . . . . . . . . . . 21
Power Management Pins . . . . . . . . . . 22
Synchronizer/Clock Interface . . . . . . . 22
Miscellaneous Pins . . . . . . . . . . . . . . . 22
Power and Ground . . . . . . . . . . . . . . . 23
IBM® Standard VGA Video
Modes . . . . . . . . . . . . . . . . . . . . . . . . . 59
Cirrus Logic Extended CRT Video
Modesa . . . . . . . . . . . . . . . . . . . . . . . . 60
IBM Standard VGA Video Modes . . . . 61
Cirrus Logic Extended LCD Video
Modea . . . . . . . . . . . . . . . . . . . . . . . . . 61
VGA Register Port Map. . . . . . . . . . . . 63
512K-Byte Memory with 4K-Byte
Granularity and VGA Mapping . . . . . . 89
Typical Power-Down Timer
Settings . . . . . . . . . . . . . . . . . . . . . . . 105
Programming the Graphics Hardware
Cursor . . . . . . . . . . . . . . . . . . . . . . . . 124
Output Loading Values Table . . . . . . 127
Bus Signal Timing (ISA Bus) . . . . . . . 130
BALE Timing (ISA Bus) . . . . . . . . . . . 132
EROM* Timing (ISA Bus) . . . . . . . . . 133
Table 7–4.
Table 7–5.
Table 7–6.
Table 7–7.
Table 7–8.
Table 7–9.
Table 7–10.
Table 7–11.
Table 7–12.
Table 7–13.
Table 7–14.
Table 7–15.
Table 7–16.
Table 7–17.
Table 7–18.
Table 7–19.
AEN Timing (ISA Bus). . . . . . . . . . . .133
PI Bus-Interface Timing. . . . . . . . . . .134
CLK1X, CLK2X Timing
(Local Bus) . . . . . . . . . . . . . . . . . . . .136
Reset Timing (Local Bus) . . . . . . . . .137
ADS#, LBA# Timing (Local Bus)
(Not Pipelined) . . . . . . . . . . . . . . . . .138
LBA#, BS16# Timing (Local Bus)
(Pipelined). . . . . . . . . . . . . . . . . . . . .139
BRDY# Delay (Local Bus). . . . . . . . .140
Read Data Timing (Local Bus) . . . . .140
Buffer Control Timing: 16-Bit Cycle
(’486 Local Bus) . . . . . . . . . . . . . . . .141
Display-Memory Bus Read Timing
(tb = MCLK) . . . . . . . . . . . . . . . . . . .142
Display-Memory Bus Write Timing
(tb = MCLK) . . . . . . . . . . . . . . . . . . .144
CAS*-Before-RAS* Refresh Timing
(Display Memory Bus). . . . . . . . . . . .146
Reset Timing . . . . . . . . . . . . . . . . . . .147
STN Monochrome and Color-Passive
LCD Interface Timing . . . . . . . . . . . .148
TFT Color Single-Scan LCD Interface
Timing, . . . . . . . . . . . . . . . . . . . . . . .150
Frequency Synthesizer Input Clock
Specification . . . . . . . . . . . . . . . . . . .152
October 1993
PRELIMINARY DATA BOOK
5
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| Information | Total 30 Pages | |
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| Download | [ CL-GD6215.PDF Datasheet ] | |
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