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ON Semiconductor - Protection Interface Circuit for PMICs

Numéro de référence NIS1050
Description Protection Interface Circuit for PMICs
Fabricant ON Semiconductor 
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NIS1050 fiche technique
NIS1050
Protection Interface Circuit
for PMICs with Integrated
OVP Control
The NIS1050 is a protection IC targeted at the latest generation of
PMICs from the leading mobile phone and UMPC chipset vendors. It
includes a highly stable low-current LDO and a low impedance power
N-Channel MOSFET.
The LDO provides a low current, five volt supply to the PMIC, and
the NFET is the external pass element for the OVIC circuit. These
stages combine with the internal PMIC to protect the charging circuit
from low-impedance overvoltage conditions that can occur from
either the AC/DC or USB supply.
The NIS1050 is available in the lowprofile 6-lead 2x2mm WDFN6
surface mount package.
Features
Lower Power Dissipation and Higher Efficiency vs. Zener Shunt
Regulator
LDO Highly Stable across Temperature, Operates Without Bypass
Capacitors
Wide 3-30 V Power Supply Voltage Input Range
LowProfile (0.75mm) 6-Lead 2x2mm WDFN6 Package
Typical Applications
Power Interface for New Generation PMICs from Leading Mobile
Phone and UMPC Chipset Vendors
http://onsemi.com
MARKING
DIAGRAMS
WDFN6, 2x2
CASE 506AN
1
PM M
PM = Specific Device Code
M = Date Code
ORDERING INFORMATION
Device
Package
Shipping
NIS1050MNTBG WDFN6 3000 / Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
3,7 NIS1050
6,8 5
LDO
2
1
4
Vbus
USB
10k
PMIC
OVP_SNS
OVP_CLAMP
OVP_CTL
Voltage
3
OverVoltage
Protection
Detector
2 V_IN_OKAY
V_REF_2
Bandgap
Reference V_REF_1
other
control
inputs
A) If okay, FET is closed
B) If not okay, FET is opened
LDO
Controller
4
VCHG
VCHG
4.7uF
Figure 1. Typical Application
www.DataSheet4U.com
5.30
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
40 15 10 35 60 85 110
TJ, JUNCTION TEMPERATURE (°C)
Figure 2. Output Voltage Variation with
Temperature
© Semiconductor Components Industries, LLC, 2009
July, 2009 Rev. 0
1
Publication Order Number:
NIS1050/D

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