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PDF K522H1HACF-B050 Data sheet ( Hoja de datos )

Número de pieza K522H1HACF-B050
Descripción 2Gb (128M x16) NAND Flash + 1Gb (64M x16 ) Mobile DDR SDRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K522H1HACF-B050 Hoja de datos, Descripción, Manual

Rev. 1.0, Oct. 2010
K522H1HACF-B050
MCP Specification
2Gb (128M x16) NAND Flash + 1Gb (64M x16 ) Mobile DDR SDRAM
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
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may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
www.DataSAhlel berta4nUd.cnoammes, trademarks and registered trademarks belong to their respective owners.
2010 Samsung Electronics Co., Ltd. All rights reserved.
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K522H1HACF-B050 pdf
K522H1HACF-B050
datasheet
3. PIN CONFIGURATION
Rev. 1.0
MCP Memory
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14
A DNU
DNU
NC
VSSn
VCCn VSSQd VDDQd VDDQd VSSQd VSSd
VDDd VSSQd
DNU
DNU
B DNU
VSSn
/REn
CLEn
/WPn
/WEn
NC
NC
NC DQ12d NC
NC VDDQd DNU
C VSSd
NC
/WEd
ALEn
/CEn
R/Bn DQ14d DQ8d DQ13d
NC
NC DQ9d UDMd VDDQd
D VDDd
/CSd
BA0d
Index
-
-
-
-
-
-
- NC NC VSSQd
E
NC
/RASd
A2d
-
VCCn
NC
NC
NC
NC
NC
-
NC DQ15d UDQSd
F /CASd
A12d
A0d
-
NC
-
-
-
- NC - DQ11d DQ10d VSSQd
G CKEd A9d BA1d - VSSn - - - - NC - VDDd VDDQd CKd
H VDDd
A11d
A7d
- IO8n
-
-
-
- IO15n - VSSd VDDQd /CKd
J A4d VSSd A5d
- IO9n
-
-
-
- IO14n - LDQSd NC VSSQd
K A6d
A10d
A3d
-
IO10n
IO11n
VCCn
VSSn
IO12n
IO13n
-
DQ2d
LDMd
DQ4d
L A13d
A8d
A1d
-
-
-
-
-
-
-
-
DQ5d
DQ7d VSSQd
M VSSd
VDDd
NC
IO5n
IO2n
IO0n
DQ6d
DQ3d
NC
NC
NC
NC DQ0d VDDQd
N DNU VCCn
NC
IO6n
IO3n VSSQd
NC
DQ1d
NC
NC
NC
NC VDDQd DNU
P DNU
DNU
VSSn
IO7n
IO4n
IO1n VDDQd VDDQd VSSQd VSSd
VDDd VSSQd
DNU
DNU
153 FBGA: Top View (Ball Down)
NAND Flash
Mobile DRAM
Power
Ground
NC/DNU
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K522H1HACF-B050 arduino
K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
Figure 1. Functional Block Diagram(x8)
VCC
VSS
A12 - A29*
X-Buffers
Latches
& Decoders
2,048M + 64M Bit for 2Gb
4,096M + 128M Bit for 4Gb DDP
NAND Flash
ARRAY
A0 - A11
Y-Buffers
Latches
& Decoders
Data Register & S/A
Y-Gating
Command
Command
Register
CE Control Logic
RE & High Voltage
WE Generator
CLE ALE WP
I/O Buffers & Latches
Global Buffers
Output
Driver
VCC
VSS
I/0 0
I/0 7
Figure 2. Array Organization(x8)
1 Block = 64 Pages
(128K + 4K) Byte
2,048 blocks for 2Gb
4,096 blocks for 4Gb DDP
2K Bytes
64 Bytes
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)Byte x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 2,048 Blocks
= 2,112 Mbits for 2Gb
8 bit 1 Device = (2K+64)B x 64Pages x 4,096 Blocks
= 4,224 Mbits for 4Gb DDP
Page Register
2K Bytes
I/O 0 ~ I/O 7
64 Bytes
I/O
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
I/O 0
A0
A8
A12
A20
A28
I/O 1
A1
A9
A13
A21
*A29
I/O 2
A2
A10
A14
A22
*L
[Table 1] Array address : (x8)
I/O 3
I/O 4
I/O 5
A3 A4 A5
A11 *L
*L
A15 A16 A17
A23 A24 A25
*L *L *L
NOTE :
Column Address : Starting Address of the Register.
w* Lwmwus.tDbeatsaeSt thoe"eLto4wU". .com
* The device ignores any additional input of address cycles than required.
* A29 is Row address for 4G DDP.
In case of 2G Mono, A29 must be set to "Low"
I/O 6
A6
*L
A18
A26
*L
I/O 7
A7
*L
A19
A27
*L
Address
Column Address
Column Address
Row Address
Row Address
Row Address
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