PDF PX1012A Data sheet ( Hoja de datos )

Número de pieza	PX1012A
Descripción	(PX1011A / PX1012A) PCI Express stand-alone X1 PHY
Fabricantes	NXP Semiconductors
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No Preview Available ! PX1011A/PX1012A PCI Express stand-alone X1 PHY Rev. 02 — 18 May 2006 Product data sheet 1. General description The PX1011A/PX1012A is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1011A/1012A PCI Express PHY is compliant to the PCI Express Base Speciﬁcation, Rev. 1.0a, and Rev. 1.1. The PX1011A/1012A includes features such as clock and data recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection, and provides superior performance to the Media Access Control (MAC) layer devices. The PX1011A/1012A is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface. Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE) speciﬁcation, enhanced and adapted for off-chip applications with the introduction of a source synchronous clock for transmit and receive data. The 8-bit data interface operates at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O interfaces available in FPGA products. The PX1011A/1012A PCI Express PHY supports advanced power management functions. The PX1011AI/PX1012AI is for the industrial temperature range (−40 °C to +85 °C). 2. Features www.DataSheet4U.net 2.1 PCI Express interface I Compliant to PCI Express Base Speciﬁcation 1.1 I Single PCI Express 2.5 Gbit/s lane I Data and clock recovery from serial stream I Serializer and De-serializer (SerDes) I Receiver detection I 8b/10b coding and decoding, elastic buffer and word alignment I Supports loopback I Supports direct disparity control for use in transmitting compliance pattern I Supports lane polarity inversion I Low jitter and Bit Error Rate (BER) 2.2 PHY/MAC interface I Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE) I Adapted for off-chip with additional synchronous clock signals (PXPIPE) I 8-bit parallel data interface for transmit and receive at 250 MHz I 2.5 V SSTL_2 class I signaling 1 page Philips Semiconductors PX1011A/PX1012A PCI Express stand-alone X1 PHY 7. Pinning information 7.1 Pinning Fig 2. Pin conﬁguration ball A1 index area PX1011A-EL1 PX1011A-EL1/G PX1011AI-EL1/G PX1012A-EL1/G PX1012AI-EL1/G 123456789 A B C D E F G H J 002aac171 Transparent top view 1 A VSS B REFCLK_P C REFCLK_N D VSS E RX_P F www.DataSheet4U.net G RX_N VSS H TX_P J TX_N 2 RXIDLE VSS VSS VSS VSS VSS VSS VSS VREFS Transparent top view. Fig 3. Ball mapping 3 RXDATA6 RXDATA7 VDDD2 VDD VDDD1 TCK TDI TDO RESET_N 4 RXDATA4 RXDATA5 VSS VDDA2 TMS TRST_N VSS TXIDLE RXPOL 5 RXDATA3 6 RXDATA1 7 RXDATAK 8 RXCLK 9 RXSTATUS0 VSS VDDD2 VDDA1 VDDD1 VDDD3 VDDD2 VSS TXCOMP RXDATA2 VSS PVT VDDD3 VDDD3 VSS PWRDWN0 PWRDWN1 RXDATA0 VSS RXSTATUS1 VDDD2 RXVALID RXSTATUS2 VSS PHYSTATUS TXDATA0 VDDD2 VSS TXDATA1 VSS TXDATA3 TXDATA2 VDDD2 RXDET_ LOOPB TXDATAK TXDATA5 VSS TXCLK TXDATA4 TXDATA6 TXDATA7 002aac210 PX1011A_PX1012A_2 Product data sheet Rev. 02 — 18 May 2006 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 5 of 32 5 Page Philips Semiconductors PX1011A/PX1012A PCI Express stand-alone X1 PHY Table 13. Summary of power management state PWRDWN[1:0] Power management state Transmitter 00b P0, normal operation on[1] 01b P0s, power saving state idle[2] 10b P1, lower power state idle[2] 11b illegal, PHY will enter P1 - [1] TXIDLE = 0 [2] TXIDLE = 1 Receiver on idle idle - TX PLL on on on - RXCLK on on on - RX PLL/CDR on on off - 8.6 Receiver detect When the PHY is in the P1 state, it can be instructed to perform a receiver detection operation to determine if there is a receiver at the other end of the link. Basic operation of receiver detection is that the MAC requests the PHY to do a receiver detect sequence by asserting RXDET_LOOPB. When the PHY has completed the receiver detect sequence, it drives the RXSTATUS signals to the value of 011b if a receiver is present, and to 000b if there is no receiver. Then the PHY will assert PHYSTATUS to indicate the completion of receiver detect operation. The MAC uses the rising edge of PHYSTATUS to sample the RXSTATUS signals and then de-asserts RXDET_LOOPB. A few cycles after the RXDET_LOOPB de-asserts, the PHYSTATUS is also de-asserted. www.DataSheet4U.net TXCLK RXDET_LOOPB PWRDWN1, PWRDWN0 RXCLK 10b PHYSTATUS RXSTATUS2, RXSTATUS1, RXSTATUS0 000b Fig 5. Receiver detect - receiver present 011b 000b 002aac173 8.7 Loopback The PHY supports an internal loopback from the PCI Express receiver to the transmitter with the following characteristics. The PHY retransmits each 10-bit data and control symbol exactly as received, without applying scrambling or descrambling or disparity corrections, with the following rules: • If a received 10-bit symbol is determined to be an invalid 10-bit code (i.e., no legal translation to a control or data value possible), the PHY still retransmits the symbol exactly as it was received. • If a SKP ordered set retransmission requires adding a SKP symbol to accommodate timing tolerance correction, any disparity can be chosen for the SKP symbol. PX1011A_PX1012A_2 Product data sheet Rev. 02 — 18 May 2006 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 11 of 32 11 Page

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