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PDF AD6641 Data sheet ( Hoja de datos )
| Número de pieza | AD6641 | |
| Descripción | 250 MHz Bandwidth DPD Observation Receiver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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250 MHz Bandwidth
DPD Observation Receiver
AD6641
FEATURES
GENERAL DESCRIPTION
SNR = 65.8 dBFS at fIN up to 250 MHz at 500 MSPS
ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
SFDR = 80 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
Excellent linearity
DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical
Integrated 16k × 12 FIFO
FIFO readback options
12-bit parallel CMOS at 62.5 MHz
6-bit DDR LVDS interface
SPORT at 62.5 MHz
SPI at 25 MHz
High speed synchronization capability
1 GHz full power analog bandwidth
Integrated input buffer
On-chip reference, no external decoupling required
Low power dissipation
695 mW at 500 MSPS
Programmable input voltage range
1.18 V to 1.6 V, 1.5 V nominal
1.9 V analog and digital supply operation
1.9 V or 3.3 V SPI and SPORT operation
Clock duty cycle stabilizer
Integrated data clock output with programmable clock and
data alignment
The AD6641 is a 250 MHz bandwidth digital predistortion
(DPD) observation receiver that integrates a 12-bit 500 MSPS
ADC, a 16k × 12 FIFO, and a multimode back end that allows
users to retrieve the data through a serial port (SPORT), the SPI
interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS
port after being stored in the integrated FIFO memory. It is opti-
mized for outstanding dynamic performance and low power
consumption and is suitable for use in telecommunications
applications such as a digital predistortion observation path
where wider bandwidths are desired. All necessary functions,
including the sample-and-hold and voltage reference, are
included on the chip to provide a complete signal conversion
solution.
The on-chip FIFO allows small snapshots of time to be captured
via the ADC and read back at a lower rate. This reduces the
constraints of signal processing by transferring the captured
data at an arbitrary time and at a much lower sample rate. The
FIFO can be operated in several user-programmable modes. In
the single capture mode, the ADC data is captured when sig-
naled via the SPI port or the use of the external FILL± pins. In
the continuous capture mode, the data is loaded continuously
into the FIFO and the FILL± pins are used to stop this operation.
APPLICATIONS
Wireless and wired broadband communications
Communications test equipment
Power amplifier linearization
FUNCTIONAL BLOCK DIAGRAM
FILL+ FILL– DUMP
CLK+
CLK–
VIN+
VIN–
CLOCK AND CONTROL
ADC
FIFO
16k × 12
PARALLEL
AND
SPORT
OUTPUTS
SPI CONTROL
REFERENCE AND DATA
VREF SCLK, SDIO, AND CSB
Figure 1.
PCLK+
PCLK–
PD[5:0]± IN DDR LVDS MODE
OR PD[11:0] IN CMOS MODE
SP_SCLK
SP_SDFS
SP_SDO
FULL
EMPTY
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
1 page  
AD6641
AC SPECIFICATIONS
AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 2.
Parameter1, 2
SNR
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
SINAD
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
SFDR
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
WORST OTHER HARMONIC (SFDR EXCLUDING SECOND AND THIRD)
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
TWO-TONE IMD
fIN1 = 119.8 MHz, fIN2 = 125.8 MHz (−7 dBFS, Each Tone)
ANALOG INPUT BANDWIDTH
Temp
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
AD6641-500
Min Typ Max
66.0
65.9
65.0
65.8
65.1
66.0
65.7
63.8
65.3
64.6
10.7
10.6
10.5
10.4
88
83
77
80
72
−92
−77
−84
−80
−72
−90
−90
−77
−85
−78
−82
1
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
GHz
1 All ac specifications tested by driving CLK+ and CLK− differentially.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
Rev. 0 | Page 5 of 28
5 Page 
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PD0– 1
PD0+ 2
PD1– 3
PD1+ 4
PD2– 5
PD2+ 6
DRVDD 7
DRGND 8
PD3– 9
PD3+ 10
PD4– 11
PD4+ 12
PD5– 13
PD5+ 14
PIN 1
INDICATOR
AD6641
TOP VIEW
(Not to Scale)
42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 VREF
30 AVDD
29 SPI_VDDIO
AD6641
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD IS THE ONLY ANALOG GROUND
CONNECTION FOR THE CHIP. IT MUST BE CONNECTED TO PCB AGND.
Figure 8. Pin Configuration for DDR LVDS Mode
Table 8. DDR LVDS Mode Pin Function Descriptions
Pin No.
Mnemonic Description
0
EPAD
Exposed Pad. The exposed pad is the only ground connection for the chip. The pad must be
connected to PCB AGND.
1
PD0−
PD0 Data Output (LSB)—Complement.
2
PD0+
PD0 Data Output (LSB)—True.
3
PD1−
PD1 Data Output—Complement.
4
PD1+
PD1 Data Output—True.
5
PD2−
PD2 Data Output—Complement.
6
PD2+
PD2 Data Output—True.
7, 24, 47
DRVDD
1.9 V Digital Output Supply.
8, 23, 48
DRGND
Digital Output Ground.
9
PD3−
PD3 Data Output—Complement.
10
PD3+
PD3 Data Output—True.
11
PD4−
PD4 Data Output—Complement.
12
PD4+
PD4 Data Output—True.
13
PD5−
PD5 Data Output (MSB)—Complement.
14
PD5+
PD5 Data Output (MSB)—True.
15
PDOR−
Overrange Output—Complement.
16
PDOR+
Overrange Output—True.
17 SP_SDO SPORT Output.
18, 19, 20, 28, 54
DNC Do Not Connect. Do not connect to this pin.
21 SP_SDFS SPORT Frame Sync Input (Slave Mode)/Output (Master Mode).
22 SP_SCLK SPORT Clock Input (Slave Mode)/Output (Master Mode).
25
SDIO
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode).
26
SCLK
Serial Port Interface Clock (Serial Port Mode).
27 CSB Serial Port Chip Select (Active Low).
29 SPI_VDDIO 1.9 V or 3.3 V SPI I/O Supply.
30, 32, 33, 34, 37, 38, 39,
41, 42, 43, 46
AVDD
1.9 V Analog Supply.
31
VREF
Voltage Reference Input/Output. Nominally 0.75 V.
35
VIN+
Analog Input—True.
36
VIN−
Analog Input—Complement.
Rev. 0 | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD6641.PDF ] | |
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