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PDF AD6643 Data sheet ( Hoja de datos )
| Número de pieza | AD6643 | |
| Descripción | Dual IF Receiver 1.8V supply voltages Internal ADC voltage reference | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Performance with NSR enabled
SNR: 76.1 dBFS in a 40 MHz band to 90 MHz at 185 MSPS
SNR: 73.6 dBFS in a 60 MHz band to 90 MHz at 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS up to 90 MHz at 185 MSPS
SFDR: 88 dBc up to 185 MHz at 185 MSPS
Total power consumption: 706 mW at 200 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
Differential analog inputs with 400 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
User-configurable, built-in self test (BIST) capability
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
GENERAL DESCRIPTION
The AD6643 is an 11-bit, 200 MSPS, dual-channel intermediate
frequency (IF) receiver specifically designed to support multi-
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of two high performance analog-to-digital
converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined
architecture with integrated output error correction logic, and
each ADC features a wide bandwidth switched capacitor sampling
network within the first stage of the differential pipeline. An
integrated voltage reference eases design considerations. A duty
cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent
performance.
Dual IF Receiver
AD6643
VIN+A
VIN–A
VCM
VIN+B
VIN–B
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
AD6643
PIPELINE 14 NOISE SHAPING 11
ADC
REQUANTIZER
PIPELINE 14 NOISE SHAPING 11
ADC
REQUANTIZER
REFERENCE
SERIAL PORT
CLOCK
DIVIDER
DCO±
D0±
D10±
OEB
SYNC
PDWN
SCLK SDIO CSB
CLK+ CLK–
NOTES
1. THE D0± TO D10± PINS REPRESENT BOTH THE CHANNEL A
AND CHANNEL B LVDS OUTPUT DATA.
Figure 1.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance in
a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the SPI.
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6643 supports enhanced SNR per-
formance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution.
The NSR block can be programmed to provide a bandwidth
of either 22% or 33% of the sample clock. For example, with a
sample clock rate of 185 MSPS, the AD6643 can achieve up to
75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and
up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.
(continued on Page 3)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
1 page  
AD6643
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI,
unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
NSR Disabled
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
NSR Enabled
22% BW Mode
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
33% BW Mode
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
Temperature
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
Min Typ
Max Unit
66.6
66.5
66.2
66.4
66.2
66.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
76.1 dBFS
75.5 dBFS
74.7 dBFS
74.2 dBFS
73.6 dBFS
73.1 dBFS
72.6 dBFS
72.1 dBFS
65.6
65.5
65.1
65.3
65.1
64.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−92 dBc
−91 dBc
−80 dBc
−88 dBc
−88 dBc
−84 dBc
92
91
80
88
88
84
dBc
dBc
dBc
dBc
dBc
dBc
−94 dBc
−94 dBc
−80 dBc
−95 dBc
−94 dBc
−93 dBc
Rev. 0 | Page 5 of 36
5 Page 
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
CLK+ 1
CLK– 2
SYNC 3
DNC 4
DNC 5
DNC 6
DNC 7
DNC 8
DNC 9
DRVDD 10
DNC 11
DNC 12
DNC 13
DNC 14
D0– (LSB) 15
D0+ (LSB) 16
AD6643
INTERLEAVED
PARALLEL
LVDS
TOP VIEW
(Not to Scale)
48 PDWN
47 OEB
46 CSB
45 SCLK
44 SDIO
43 OR+
42 OR–
41 D10+ (MSB)
40 D10– (MSB)
39 D9+
38 D9–
37 DRVDD
36 D8+
35 D8–
34 D7+
33 D7–
AD6643
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE
MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 4. Pin Configuration (Top View), LFCSP Interleaved Parallel LVDS
Table 8. Pin Function Descriptions for the Interleaved Parallel LVDS Mode
Pin No.
Mnemonic Type
Description
ADC Power Supplies
10, 19, 28, 37
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54, 59, 60, 63, 64 AVDD
Supply
Analog Power Supply (1.8 V Nominal).
4 to 9, 11 to 14, 55, 56, 58
DNC
Do Not Connect. Do not connect to these pins.
0
AGND,
Ground
Analog Ground. The exposed thermal paddle on the bottom of the
Exposed
package provides the analog ground for the device. This exposed paddle
Paddle
must be connected to ground for proper operation.
ADC Analog
51
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
52
VIN−A
Input
Differential Analog Input Pin (−) for Channel A.
62
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
61
VIN−B
Input
Differential Analog Input Pin (−) for Channel B.
57
VCM
Output
Common-Mode Level Bias Output for Analog Inputs. This pin should be
decoupled to ground using a 0.1 μF capacitor.
1
CLK+
Input
ADC Clock Input—True.
2
CLK−
Input
ADC Clock Input—Complement.
Digital Input
3
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Digital Outputs
15
D0− (LSB) Output
Channel A/Channel B LVDS Output Data 0—True.
16
D0+ (LSB) Output
Channel A/Channel B LVDS Output Data 0—Complement.
18
D1+
Output
Channel A/Channel B LVDS Output Data 1—True.
17
D1−
Output
Channel A/Channel B LVDS Output Data 1—Complement.
21
D2+
Output
Channel A/Channel B LVDS Output Data 2—True.
20
D2−
Output
Channel A/Channel B LVDS Output Data 2—Complement.
23
D3+
Output
Channel A/Channel B LVDS Output Data 3—True.
22
D3−
Output
Channel A/Channel B LVDS Output Data 3—Complement.
Rev. 0 | Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD6643.PDF ] | |
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