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PDF AD6649 Data sheet ( Hoja de datos )
| Número de pieza | AD6649 | |
| Descripción | IF Diversity Receiver | |
| Fabricantes | Analog Devices | |
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IF Diversity Receiver
AD6649
FEATURES
APPLICATIONS
SNR = 73.0 dBFS in a 95 MHz bandwidth at
185 MHz AIN and 245.76 MSPS
SFDR = 85 dBc at 185 MHz AIN and 250 MSPS
Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS
AIN and 250 MSPS
Total power consumption: 1 W with fixed-frequency NCO,
95 MHz FIR filter
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Integrated dual-channel ADC
Sample rates of up to 250 MSPS
IF sampling frequencies to 400 MHz
Internal ADC voltage reference
Flexible input range
1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital processor
32-bit complex numerically controlled oscillator (NCO)
FIR filter with 2 modes
Real output from an fS/4 output NCO
Amplitude detect bits for efficient AGC implementation
Energy saving power-down modes
Decimated, interleaved real LVDS data outputs
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
General-purpose software radios
Broadband data applications
GENERAL DESCRIPTION
The AD6649 is a mixed-signal intermediate frequency (IF) receiver
consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital
downconverter (DDC). The AD6649 is designed to support
communications applications, where low cost, small size, wide
bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided to
compensate for variations in the ADC clock duty cycle, allowing
the converters to maintain excellent performance.
FUNCTIONAL BLOCK DIAGRAM
AVDD
FDA
DRVDD
VIN+A
VIN–A
THRESHOLD DETECT
ADC
DC
CORRECTION
I SELECTABLE
FIR
FILTER
Q SELECTABLE
FIR
FILTER
AD6649
DIGITAL
INTERLEAVING
OR+
OR–
D13+/D13–
D0+/D0–
REFERENCE
32-BIT
TUNING NCO
VIN–B
VIN+B
DC
CORRECTION
ADC
THRESHOLD DETECT
Q SELECTABLE
FIR
FILTER
I SELECTABLE
FIR
FILTER
fS/4
NCO
DIVIDE 1
TO 8
DUTY
CYCLE
STABILIZER
DCO
GENERATION
MULTICHIP
SYNC
PROGRAMMING DATA
SPI
CLK+
CLK–
DCO+
DCO–
SYNC
AGND
FDB
PDWN
OEB
SDIO SCLK CSB
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
1 page  
AD6649
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input,1 1.75 V p-p full-scale input range,
DCS enabled, NCO enabled, FIR filter enabled, unless otherwise noted.
Table 2.
Parameter2
SIGNAL-TO-NOISE RATIO (SNR)3
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 184.12 MHz, 187.12 MHz (−7 dBFS)
CROSSTALK4
ANALOG INPUT BANDWIDTH
Temperature
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
Min Typ
74.5
74.2
73.9
73.4
70.9
72.9
73.4
73.0
72.3
71.7
68.7
71.0
−92
−88
−85
−85
−89
92
88
85
85
80
84
−95
−94
−93
−93
−84
88
95
1000
Max Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
−80 dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−80 dBc
dBc
dBc
dB
MHz
1 A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the
tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters
section for more details.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
3 SNR specifications are for filtered 95 MHz bandwidth.
4 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.
Rev. 0 | Page 5 of 40
5 Page 
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
CLK+ 1
CLK– 2
SYNC 3
FDA 4
FDB 5
DNC 6
DNC 7
D0– (LSB) 8
D0+ (LSB) 9
DRVDD 10
D1– 11
D1+ 12
D2– 13
D2+ 14
D3– 15
D3+ 16
AD6649
TOP VIEW
(Not to Scale)
48 PDWN
47 OEB
46 CSB
45 SCLK
44 SDIO
43 OR+
42 OR–
41 D13+ (MSB)
40 D13– (MSB)
39 D12+
38 D21–
37 DRVDD
36 D11+
35 D11–
34 D10+
33 D10–
AD6649
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG
GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 4. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
10, 19, 28, 37
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54, 59, 60, 63, 64
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
6, 7, 55, 56, 58
DNC
Do Not Connect. Do not connect to this pin.
0
AGND,
Ground
Analog Ground. The exposed thermal paddle on the bottom of the
Exposed Paddle
package provides the analog ground for the part. This exposed
paddle must be connected to ground for proper operation.
ADC Analog
51
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
52
VIN−A
Input
Differential Analog Input Pin (−) for Channel A.
62
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
61
VIN−B
Input
Differential Analog Input Pin (−) for Channel B.
57
VCM
Output
Common-Mode Level Bias Output for Analog Inputs. This pin
should be decoupled to ground using a 0.1 μF capacitor.
1
CLK+
Input
ADC Clock Input—True.
2
CLK−
Input
ADC Clock Input—Complement.
ADC Fast Detect Outputs
4
FDA
Output
Channel A Fast Detect Indicator (CMOS Levels).
5
FDB
Output
Channel B Fast Detect Indicator (CMOS Levels).
Digital Input
3
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Digital Outputs
9
D0+ (LSB)
Output
Channel A/Channel B LVDS Output Data 0—True.
8
D0− (LSB)
Output
Channel A/Channel B LVDS Output Data 0—Complement.
12
D1+
Output
Channel A/Channel B LVDS Output Data 1—True.
11
D1−
Output
Channel A/Channel B LVDS Output Data 1—Complement.
14
D2+
Output
Channel A/Channel B LVDS Output Data 2—True.
13
D2−
Output
Channel A/Channel B LVDS Output Data 2—Complement.
16
D3+
Output
Channel A/Channel B LVDS Output Data 3—True.
Rev. 0 | Page 11 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD6649.PDF ] | |
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