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ZVP2106C fiches techniques PDF

Zetex Semiconductors - P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

Numéro de référence ZVP2106C
Description P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET
Fabricant Zetex Semiconductors 
Logo Zetex Semiconductors 





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ZVP2106C fiche technique
P-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 60 Volt VDS
* RDS(on)=5
ZVP2106C
REFER TO ZVP2106A FOR GRAPHS
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at Tamb=25°C
Pulsed Drain Current
Gate Source Voltage
Power Dissipation at Tamb=25°C
Operating and Storage Temperature Range
SYMBOL
VDS
ID
IDM
VGS
Ptot
Tj:Tstg
GD
S
E-Line
TO92 Compatible
VALUE
-60
-280
-4
± 20
700
-55 to +150
UNIT
V
mA
A
V
mW
°C
ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BVDSS
-60
V ID=-1mA, VGS=0V
Gate-Source Threshold
Voltage
VGS(th) -1.5 -3.5 V
ID=-1mA, VDS= VGS
Gate-Body Leakage
Zero Gate Voltage Drain
Current
On-State Drain Current(1)
Static Drain-Source
On-State Resistance (1)
IGSS
IDSS
ID(on)
RDS(on)
-1
20
-0.5
-100
5
nA
µA
µA
A
VGS=± 20V, VDS=0V
VDS=-60 V, VGS=0
VDS=-48 V, VGS=0V, T=125°C(2)
VDS=-18 V, VGS=-10V
VGS=-10V,ID=-500mA
Forward Transconductance gfs
(1)(2)
150
mS VDS=-18V,ID=-500mA
Input Capacitance (2)
Common Source Output
Capacitance (2)
Ciss
Coss
100 pF
60 pF
VDS=-18V, VGS=0V, f=1MHz
Reverse Transfer
Capacitance (2)
Crss
20 pF
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
td(on)
tr
td(off)
tf
7 ns
15 ns VDD-18V, ID=-500mA
12 ns
15 ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle 2% (2) Sample test.
(3) Switching times measured with 50source impedance and <5ns rise time on a pulse generator
3-420

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