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PDF Q42724211000200 Data sheet ( Hoja de datos )

Número de pieza Q42724211000200
Descripción Real Time Clock Module
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No Preview Available ! Q42724211000200 Hoja de datos, Descripción, Manual

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Order code
90-0362
Manufacturer code
Q42724211000200
DATA SHEET
Description
RTC-72421B REAL TIME CLOCK DIL18 RC
The enclosed information is believed to be correct, Information may change without noticedue to
product improvement. Users should ensure that the product is suitable for their use. E. & O. E.
Page 1 of 27
Revision A
20/02/2007
Sales: 01206 751166
Technical: 01206 835555
Fax: 01206 751188
www.rapidonline.com
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Q42724211000200 pdf
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RTC - 72421 / 72423
4-BIT PARALLEL INTERFACE REAL TIME CLOCK MODULE
RTC - 72421 / 72423
Built-in crystal unit removes need for adjustment and reduces installation costs
Microprocessor bus compatible ( tWW, tRD = 120 ns )
Use of C-MOS IC enables low current consumption ( 5 µA Max., at VDD = 2.0 V )
Compatibility with Intel CPU bus
Address latch enable (ALE) pin compatible with multiplex bus CPUs
Time (hours, minutes, seconds) and calendar (year, month, day) counter
24-hour/12-hour switchover and automatic leap-year correction functions
Fixed-period interrupt function
30-seconds correction (adjustment) function
Stop, start, and reset functions
Battery back-up function
Same mounting conditions as general-purpose SMD ICs possible (RTC-72423)
Pins and functions compatible with the SMC-5242 series
! Overview
The RTC-72421/RTC-72423 module is a real time clock that can be connected directly to a microprocessor's bus. Its built-in crystal
unit enables highly accurate time-keeping with no physical access required for adjustment and, since there is no need to connect
external components, mounting and other costs can be reduced.
In addition to its time and calendar functions, the RTC-72421/RTC-72423 enables the use of 30-seconds correction and fixed-
period interrupt functions.
The RTC-72421/RTC-72423 module is ideally suited for applications requiring timing management, such as personal computers,
dedicated word-processors, fax machines, multi-function telephones, and sequencers.
! Block diagram
D3
D2 Gate
D1
D0
WR
RD Gate
OSC
Counter
RTC-72421/72423
RESET
bit
30sec ADJ
bit
STOP
bit
HOLD BUSY
bit bit
S1 S10
MI1 MI10
24/12
bit
H1 H10
W
A3
A2
A1
A0
CS0
Latch
S1 to CF
Decoder
D1 D10
MO1 MO10
Y1 Y10
Output Selector
ALE
CS1
64 Hz
1 Second carry
CD CE CF 1 Minute carry
1 Hour carry
STD.P
Page 1
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Q42724211000200 arduino
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RTC - 72421 / 72423
! Registers
1. Register table
Address
(Hex)
A3 A2 A1 A0 Register
name
0
0000
S1
1
0001
S10
2
0010
MI1
3
0011
MI10
4
0100
H1
5
0101
H10
6
0110
D1
7
0111
D10
8
1000
MO1
9
1001
MO10
A
1010
Y1
B
1011
Y10
C
1100
W
D
1101
CD
E
1110
CE
F
1111
CF
D3
s8
*
mi8
*
h8
*
d8
*
mo8
*
y8
y80
*
30s ADJ
t1
TEST
Data
D2 D1
s4 s2
s40 s20
mi4 mi2
mi40
mi20
h4 h2
PM/AM
h20
d4 d2
* d20
mo4
mo2
**
y4 y2
y40 y20
w4 w2
IRQ FLAG BUSY
t0
24/12
ITRPT/
STND
STOP
D0
s1
s10
mi1
mi10
h1
h10
d1
d10
mo1
mo10
y1
y10
w1
HOLD
MASK
RESET
Count
(BCD)
0 to 9
0 to 5
0 to 9
0 to 5
0 to 9
0 to1 or 2
0 to 9
0 to 3
0 to 9
0 to 1
0 to 9
0 to 9
0 to 6
Remarks
1-second digit register
10-seconds digit register
1-minute digit register
10-minute digit register
1-hour digit register
10-hours digit register
1-day digit register
10-days digit register
1-month digit register
10-months digit register
1-year digit register
10-years digit register
Day-of-the-week register
Control register D
Control register E
Control register F
2. Notes
The counts at addresses 0 to C are all positive logic. Therefore, a register bit that is 1 appears as a high-level signal on the data bus.
Data representation is BCD.
Do not set an impossible date or time in the RTC. If such a value is set, the effect is unpredictable.
When the power is turned on (before the RTC is initialized), the state of all bits is undefined. Therefore, write to all registers after
power-on, to set initial values. For details of the initialization procedure, see "Using the RTC-72421/RTC-72423".
The TEST bit of control register F is used by EPSON for testing. Operation cannot be guaranteed if 1 is written to this bit, so make
sure that it is set to 0 during power-on initialization.
3. Functions of register bits (overview)
Bit name
* mark
Seconds to year digit
Day-of-the-week digit
Function
Not used. Writing to this bit has no effect; reading it always returns 0.
All written BCD code.
This is special (base 7) counter that increments each time the day digits are incremented. It counts from 0 to 6. Since the value in the
counter bears no relationship to the day of the week, the user can choose the coding that relates the counter value to the day of the
week. The following is just one example of this relationship.
Count
Day
0
Sunday
1234
Monday Tuesday Wednesday Thursday
5
Friday
6
Saturday
PM/AM
30-seconds ADJ
IRQ FLAG
BUSY
HOLD
t1,t0
ITRPT/STND
MASK
TEST
24/12
STOP
RESET
The PM/AM bit is 1 for p.m. times; 0 for a.m. times. This bit is valid only for 12-hour-clock mode (when the 24/12 bit is 0); in 24-hour-
clock mode (when the 24/12 bit is 1), this bit is always 0.
Writing 1 to this bit executes a 30-seconds correction.
The IRQ FLAG bit is set to 1 when an interrupt request is generated in fixed-period interrupt mode. Writing 0 to this bit clears it. Note
that it is possible to write 1 to this bit, but this will have no effect.
In fixed-period pulse output mode, this bit is at 1 while the pulse output is active(While the STD.P pin output is low), and is
automatically cleared when pulse output ends. Writing 0 to this bit while pulse output is active forcibly cancels the pulse output.
Use the BUSY bit when accessing data in the S1 to W registers. This bit is set to 1 during the incrementation cycle of the S1 to W
registers, and is set to 0 otherwise. When the BUSY bit is 1, access to the S1 to W registers is inhibited.
Note that the HOLD bit must also be used when accessing the S1 to W registers. The BUSY bit is always 1 when the HOLD bit is 0.
There is no need to check the BUSY bit when accessing the control registers (CD, CE and CF).
When 1 has been written to the HOLD bit, the status of the BUSY bit can be checked. While the HOLD bit is 1, any incrementation of
the digits is held just once. (The incrementation is held only once, even if the HOLD bit remains at 1 for two or more seconds.)
Clear the HOLD bit to 0 by forcing the CS1 pin low.
These bits set the timing for fixed-period pulse output and interrupts (1/64 seconds, 1 second, 1minute or 1 hour).
The ITRPT/STND bit sets fixed-period pulse output mode and fixed-period interrupt mode. Write 1 to this bit to set interrupt(INRPT)
mode; when write 0 to it to set pulse output(STND) mode.
The MASK bit disables fixed-period pulse output and fixed-period interrupts. Write 1 to this bit to mask and inhibit these modes; write
0 to it to enable these modes.
The TEST bit is used by EPSON for test purposes. Operation cannot be guaranteed if 1 is written to this bit, so make sure that it is
set to 0 during power-on initialization.
The 24/12 bit switches between 24-hour clock and 12-hour clock. Write 1 to this bit to set 24-hour mode; write 0 to it to set 12-hour
mode. When the 24/12 bit is set, both the timer registers and the timer mode must be reset to match. Note that the h20 bit of the H10
register is always in 12-hour-clock mode.
The STOP bit sets an inhibition on clock operation in 8192 Hz steps which are divisions of the 1 second signal from the RTC’s
internal 32768 Hz oscillation source. The clock is inhibited when the STOP bit is 1, and released again when it becomes 0. The
internal oscillation circuit continues to operate even when the STOP bit is 1.
The RESET bit resets the part of the counter that is below one second. Write 1 to this bit to reset; 0 to release the reset.
The RESET bit set to 0 when the CS1 pin goes low.
Page 7
ETM17E-01
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