DataSheet.es    


PDF SX1233 Data sheet ( Hoja de datos )

Número de pieza SX1233
Descripción High Bit Rate Transceiver
Fabricantes Semtech Corporation 
Logotipo Semtech Corporation Logotipo



Hay una vista previa y un enlace de descarga de SX1233 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! SX1233 Hoja de datos, Descripción, Manual

SX1233www.DataSheet.co.kr
ADVANCED COMMUNICATIONS & SENSING
SX1233 High Bit Rate Transceiver
Low Power Integrated UHF Transceiver
DATASHEET
VBAT1&2
VR_ANA
VR_DIG
Power Distribution System
RC
Oscillator
RFIO
LNA
Σ/Δ
Single to
Mixers
Modulators
Differential
RESET
SPI
SX1233
GND
VR_PA
PA_BOOST
PA0
Ramp &
Control
PA1&2
Tank
Inductor
Loop
Filter
Division by
2, 4 or 6
Frac-N PLL
Synthesizer
XO
32 MHz
XTAL
RSSI
AFC
GND
RXTX
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
GENERAL DESCRIPTION
The SX1233 is a highly integrated RF transceiver capable of
operation over a wide frequency range, including the 433,
868 and 915 MHz license-free ISM (Industry Scientific and
Medical) frequency bands. Its highly integrated architecture
allows for a minimum of external components whilst
maintaining maximum design flexibility. All major RF
communication parameters are programmable and most of
them can be dynamically set. The SX1233 offers the unique
advantage of programmable narrow-band and wide-band
communication modes without the need to modify external
components. The SX1233 is optimized for low power
consumption while offering high RF output power and
channelized operation. TrueRF™ technology enables a low-
cost external component count (elimination of the SAW
filter) whilst still satisfying ETSI and FCC regulations.
SX1233 is pin to pin compatible with SX1231 and SX1239.
APPLICATIONS
Š Automated Meter Reading
Š Wireless Sensor Networks
Š Home and Building Automation
Š Wireless Alarm and Security Systems
Š Industrial Monitoring and Control
KEY PRODUCT FEATURES
Š Programmable bit rate up to 600kbps (FSK)
Š High Sensitivity: down to -120 dBm at 1.2 kbps
Š High Selectivity: 16-tap FIR Channel Filter
Š Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,
80 dB Blocking Immunity, no Image Frequency response
Š Low current: Rx = 16 mA, 100nA register retention
Š Programmable Pout: -18 to +17 dBm in 1dB steps
Š Constant RF performance over voltage range of chip
Š Fully integrated synthesizer with a resolution of 61 Hz
Š FSK, GFSK, MSK, GMSK and OOK modulations
Š Built-in Bit Synchronizer performing Clock Recovery
Š Incoming Sync Word Recognition
Š 115 dB+ Dynamic Range RSSI
Š Automatic RF Sense with ultra-fast AFC
Š Packet engine with CRC, AES-128 encryption and 66-
byte FIFO
Š Built-in temperature sensor and Low Battery indicator
ORDERING INFORMATION
MARKETS
Š Europe: EN 300-220-1
Š North America: FCC Part 15.247, 15.249, 15.231
Š Narrow Korean and Japanese bands
Part Number
SX1233IMLTRT
Delivery
Tape & Reel
MOQ / Multiple
3000 pieces
Š QFN 24 Package - Operating Range [-40;+85°C]
Š Pb-free, Halogen free, RoHS/WEEE compliant product
Rev 3.April 2010
Page 1
www.semtech.com
Datasheet pdf - http://www.DataSheet4U.net/

1 page




SX1233 pdf
SX1233www.DataSheet.co.kr
ADVANCED COMMUNICATIONS & SENSING
Table of contents
Section
DATASHEET
Page
Index of Figures
Figure 1. Block Diagram .................................................................................................................................................8
Figure 2. Pin Diagram .....................................................................................................................................................9
Figure 3. Marking Diagram .............................................................................................................................................9
Figure 4. TCXO Connection .........................................................................................................................................16
Figure 5. Transmitter Block Diagram ............................................................................................................................19
Figure 6. Receiver Block Diagram ................................................................................................................................23
Figure 7. AGC Thresholds Settings ..............................................................................................................................24
Figure 8. Cordic Extraction ...........................................................................................................................................28
Figure 9. OOK Peak Demodulator Description .............................................................................................................28
Figure 10. Floor Threshold Optimization ......................................................................................................................29
Figure 11. Bit Synchronizer Description .......................................................................................................................30
Figure 12. FEI Process .................................................................................................................................................31
Figure 13. Optimized AFC (AfcLowBetaOn=1) ............................................................................................................32
Figure 14. Temperature Sensor Response ..................................................................................................................33
Figure 15. Tx Startup, FSK and OOK ...........................................................................................................................36
Figure 16. Rx Startup - No AGC, no AFC .....................................................................................................................37
Figure 17. Rx Startup - AGC, no AFC ..........................................................................................................................37
Figure 18. Rx Startup - AGC and AFC .........................................................................................................................37
Figure 19. Listen Mode Sequence (no wanted signal is received) ...............................................................................39
Figure 20. Listen Mode Sequence (wanted signal is received) ....................................................................................41
Figure 21. Auto Modes of Packet Handler ....................................................................................................................42
Figure 22. SX1233 Data Processing Conceptual View ................................................................................................43
Figure 23. SPI Timing Diagram (single access) ...........................................................................................................44
Figure 24. FIFO and Shift Register (SR) ......................................................................................................................45
Figure 25. FifoLevel IRQ Source Behavior ...................................................................................................................46
Figure 26. Sync Word Recognition ...............................................................................................................................47
Figure 27. Continuous Mode Conceptual View ............................................................................................................49
Figure 28. Tx Processing in Continuous Mode .............................................................................................................49
Figure 29. Rx Processing in Continuous Mode ............................................................................................................50
Figure 30. Packet Mode Conceptual View ...................................................................................................................51
Figure 31. Fixed Length Packet Format .......................................................................................................................52
Figure 32. Variable Length Packet Format ...................................................................................................................52
Figure 33. Unlimited Length Packet Format .................................................................................................................53
Figure 34. CRC Implementation ...................................................................................................................................58
Figure 35. Manchester Encoding/Decoding .................................................................................................................58
Figure 36. Data Whitening ............................................................................................................................................59
Figure 37. POR Timing Diagram ..................................................................................................................................75
Figure 38. Manual Reset Timing Diagram ....................................................................................................................76
Rev 3.April 2010
Page 5
www.semtech.com
Datasheet pdf - http://www.DataSheet4U.net/

5 Page





SX1233 arduino
SX1233www.DataSheet.co.kr
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
2. Electrical Characteristics
2.1. ESD Notice
The SX1233 is a high performance radio frequency device. It satisfies:
Š Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model) on all pins.
Š Class B of the JEDEC standard JESD22-A115-A (Machine Model) on all pins.
Š Class IV of the JEDEC standard JESD22-C101C (Charged Device Model) on pins 2-3-21-23-24, Class III on all other
pins.
It should thus be handled with all the necessary ESD precautions to avoid any permanent damage.
2.2. Absolute Maximum Ratings
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 2 Absolute Maximum Ratings
Symbol
VDDmr
Tmr
Tj
Pmr
Supply Voltage
Temperature
Junction temperature
RF Input Level
Description
Min Max Unit
-0.5 3.9 V
-55
+115
°C
-
+125
°C
- +6 dBm
2.3. Operating Range
Table 3 Operating Range
Symbol
VDDop
Top
Clop
ML
Description
Supply voltage
Operational temperature range
Load capacitance on digital ports
RF Input Level
Min Max Unit
1.8 3.6 V
-40 +85 °C
- 25 pF
- 0 dBm
Rev 3.April 2010
Page 11
www.semtech.com
Datasheet pdf - http://www.DataSheet4U.net/

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet SX1233.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
SX1230Integrated Transmitter ICSemtech Corporation
Semtech Corporation
SX1231Low Power Integrated UHF TransceiverSemtech Corporation
Semtech Corporation
SX1231JLow Power Integrated UHF TransceiverSemtech Corporation
Semtech Corporation
SX1231JIMLTRTLow Power Integrated UHF TransceiverSemtech Corporation
Semtech Corporation

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar