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PDF LE24CBK222 Data sheet ( Hoja de datos )
| Número de pieza | LE24CBK222 | |
| Descripción | Two Wire Serial Interface EEPROM | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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www.DataSheet.co.kr
Ordering number : EN*A1811A
LE24CBK222
CMOS IC
Triple port EEPROM
Two Wire Serial Interface
(2K+2K EEPROM)
Overview
The triple port EEPROM series consists of two independent banks, and each bank can be controlled separately using
dedicated control pins. The EEPROM also features a control port, which is a third pin separate from the pins used for the
banks, and by accessing the memory areas from this control port, the two-bank configuration (2K bits + 2K bits) can be
used as a pseudo-one-bank configuration (4K bits). Together with the 16-byte page write function, this enables a
reduction in the number of factory write processes.
Furthermore, the EEPROM has a configuration area which is separate from the 2K-bit + 2K-bit area, and by using the
settings stored in this configuration area, it is possible to change the slave address for each port and to set read/write
protection for each port.
This product incorporates SANYO's high performance CMOS EEPROM technology and realizes high-speed operation
and high-level reliability. The interface of this product is compatible with the I2C bus protocol, making it ideal as a
nonvolatile memory for small-scale parameter storage.
In addition, this product also supports DDC2TM, so it can also be used as an EDID data storage memory for display
equipment.
Functions
• Capacity
: Bank1:2K bits (256 × 8 bits) + Bank2:2K bits (256 × 8 bits)
+ configuration area: 128 bits (16 × 8 bits), 4224 bits in total
• Single supply voltage
• Interface
: 2.5V to 5.5V
: Two wire serial interface (I2C Bus*), VESA DDC2TM compliant** 3-port access
• Operating clock frequency : 400kHz (max)
• Low power consumption : Standby: 5μA (max)
: One-bank read: 0.5 mA (max.), Two-bank simultaneous read: 1.0 mA (max.)
* : I2C Bus is a trademark of Philips Corporation.
Continued on next page.
** : DDC and EDID are trademarks of Video Electronics Standard Association (VESA).
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
10511 SY/92910 SY No.1811-1/20
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
Standard Mode
Parameter
Slave mode SCL clock frequency
SCL clock low time
SCL clock high time
SDA output delay time
SDA data output hold time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
SCL, SDA rise time
SCL, SDA fall time
Bus release time
Noise suppression time
Write cycle time
LE24CBK222
Symbol
fSCLS
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tBUF
tSP
tWC
VDD=2.5V to 5.5V
min typ
4700
4000
100
100
4700
4000
250
0
4000
4700
max
100
3500
1000
300
100
5
unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Bus Timing
SCL
SDA/IN
SDA/OUT
tSU.STA
tF
tHIGH
tLOW
tHD.STA
tHD.DAT
tHD.STA
tAA tDH
tR
tSU.STO
tBUF
tSP
tSP
Write Timing
SCL
SDA
D0
Write data
Acknowledge
tWC
Stop
condition
Start
condition
No.1811-5/20
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
LE24CBK222
8 EEPROM write operation
8-1. Byte writing
When the EEPROM receives the 7-bit device address and write command code “0” after the start condition, it
generates an acknowledge signal. After this, if it receives the 8-bit word address, generates an acknowledge signal,
receives the 8-bit write data, generates an acknowledge signal and then receives the stop condition, the internal write
operation of the EEPROM in the designated memory address will start. Rewriting is completed in the tWC period
after the stop condition. During an EEPROM internal write operation, no input is accepted and no acknowledge
signals are generated.
Device Address
Word Address
SDA
S0
1 0 1 0 S2 S1 / W
A8
A7 A6 A5 A4 A3 A2 A1 A0
ACK
R/W
S2, S1, S0 : Slave Address
A8 : Bank selecting address used during control port access
Data
D7 D6 D5 D4 D3 D2 D1 D0
ACK
ACK
Access from master
8-2. Page writing
This product enables pages with up to 16 bytes to be written. The basic data transfer procedure is the same as for byte
writing: Following the start condition, the 7-bit device address and write command code “0,” word address (n), and
data (n) are input in this order while confirming acknowledge “0” every 9 bits. The page write mode is established if,
after data (n) is input, the write data (n+1) is input without inputting the stop condition. After this, the write data
equivalent to the largest page size can be received by a continuous process of repeating the receiving of the 8-bit
write data and generating the acknowledge signals.
At the point when the write data (n+1) has been input, the lower 4 bits (A0-A3) of the word addresses are
automatically incremented to form the (n+1) address. In this way, the write data can be successively input, and the
word address on the page is incremented each time the write data is input. If the write data exceeds 16 bytes or the
last address of the page is exceeded, the word address on the page is rolled over. Write data will be input into the
same address two or more times, but in such cases the write data that was input last will take effect. Finally, the
EEPROM internal write operation corresponding to the page size for which the write data is received starts from the
designated memory address when the stop condition is received.
SDA
Device Address
Word Address
S0
1 0 1 0 S2 S1 / W
A8
A7 A6 A5 A4 A3 A2 A1 A0
ACK
R/W
Data(n)
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Data(n+1)
D7 D6 D1 D0
ACK
ACK
Data(n+x)
D7 D6 D1 D0 D7 D6 D1 D0
D7 D6 D1 D0 D7 D6 D1 D0
ACK
S2, S1, S0 : Slave Address
A8 : Bank selecting address used during control port access
ACK
ACK
Access from master
No.1811-11/20
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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