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PDF W681512 Data sheet ( Hoja de datos )
| Número de pieza | W681512 | |
| Descripción | SINGLE-CHANNEL VOICEBAND CODEC | |
| Fabricantes | Nuvoton Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de W681512 (archivo pdf) en la parte inferior de esta página. Total 34 Páginas | ||
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W681512
SINGLE-CHANNEL
VOICEBAND CODEC
www.DataSheet.co.kr
Data Sheet
Revision C17
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
W681512
11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 28
12. PACKAGE SPECIFICATION........................................................................................................... 30
12.1. 20L SOG (SOP)-300mil ............................................................................................................. 30
12.2. 20L SSOP-209 mil ..................................................................................................................... 31
12.3. 20L TSSOP - 4.4X6.5mm .......................................................................................................... 32
13. ORDERING INFORMATION ........................................................................................................... 33
14. VERSION HISTORY ....................................................................................................................... 34
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-5-
Publication Release Date: January 2011
Revision C17
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
W681512
7.4.2. Short Frame Sync
The W681512 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is
HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge
of the bit-clock, the W681512 starts clocking out the data on the PCMT pin, which will also change
from high to low impedance state. The data transmit pin PCMT will go back to the high impedance
state halfway through the LSB. The Short Frame Sync operation of the W681512 is based on an 8-bit
data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after
the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine
whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse.
To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every
power down state. More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface
consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects
channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data
clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.
The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted
consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is
transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.
7.4.4. Interchip Digital Link (IDL)
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The IDL interface mode is selected when the BCLKR pin is connected to VDD for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface
consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR
pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the
first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK cycle
long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after the IDL
SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK after the
IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the IDL CLK
after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not used for
data transmission and also in the time slot of the unused channel. For more timing information, see the
timing section.
7.4.5. System Timing
The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz
master clock rates. The system clock is supplied through the master clock input MCLK and can be
derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and 8
kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency
versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is LOW for
the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the
W681512 will enter the low power standby mode. Another way to power down is to set the PUI pin to
LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the
Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will
become low impedance.
- 11 -
Publication Release Date: January 2011
Revision C17
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 34 Páginas | |
| PDF Descargar | [ Datasheet W681512.PDF ] | |
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