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PDF SH2A-FPU Data sheet ( Hoja de datos )
| Número de pieza | SH2A-FPU | |
| Descripción | 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas | |
| Logotipo |  |
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To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
www.DataSheet.co.kr
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
Main Revisions for this Edition
Item
1.1 Features
Page
1
2.2.2 Control
Registers
5
(1) Status Register,
SR
3.1.1 Exception
16
Handling Types and
Priority
Table 3.1 Exception
Types and Priority
3.1.2 Exception
18
Handling Operation
(2) Address Error,
RAM Error, Register
Bank Error, Interrupt,
or Instruction
Exception Handling
3.3.1 Address Error 22
Sources
Table 3.5 Bus
Cycles and Address
Errors
3.6.3 Interrupt
26
Exception Handling
Revision (See Manual for Details)
Description amended
The SH-2A/SH2A-FPU is a 32-bit RISC (reduced instruction set
computer) microprocessor that is upward-compatible with the SH-
1, SH-2, and SH-2E at the object code level.
Description amended
(32-bit, initial value =0000 0000 0000 0000 00X0 00XX 1111
00XX)
Note amended
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR,
RTS, RTE,
BF/S, BT/S, BSRF, BRAF
.
Description amended
⋅⋅⋅ and the vector table address offset of the interrupt exception
handling to be executed,⋅⋅⋅
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Table amended
Bus Cycle
Type
Bus Master
Data
CPU or
read/write DMAC
Bus Cycle Operation
Double longword data accessed from double
longword boundary
Double longword data accessed from other
than double longword boundary
Address Error
Occurrence
No error (normal)
Address error
Description amended
⋅⋅⋅ and the vector table address offset of the interrupt exception
handling to be executed,⋅⋅⋅
Rev. 3.00 Jul 08, 2005 page iii of xiv
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
6.3.4 BLD ........... Bit LoaD ...................................... Bit Manipulation Instruction ... 94
6.3.5 BLDNOT ... Bit LoaDNOT .............................. Bit Manipulation Instruction ... 96
6.3.6 BOR ........... Bit OR ......................................... Bit Manipulation Instruction ... 98
6.3.7 BORNOT ... Bit ORNOT ................................. Bit Manipulation Instruction ... 100
6.3.8 BSET ......... Bit SET ........................................ Bit Manipulation Instruction ... 102
6.3.9 BST ............ Bit STore ..................................... Bit Manipulation Instruction ... 104
6.3.10 BXOR ........ Bit exclusive OR ......................... Bit Manipulation Instruction ... 106
6.3.11 CLIPS ........ CLIP as Signed ............................ Arithmetic Instruction ............. 108
6.3.12 CLIPU ........ CLIP as Unsigned ........................ Arithmetic Instruction ............. 111
6.3.13 DIVS .......... DIVide as Signed ........................ Arithmetic Instruction ............. 113
6.3.14 DIVU ......... DIVide as Unsigned .................... Arithmetic Instruction ............. 114
6.3.15 FMOV ........ Floating-point MOVe .................. Floating-Point Instruction........ 115
6.3.16 JSR/N ......... Jump to SubRoutine with No delay slot
...................................................... Branch Instruction ................... 118
6.3.17 LDBANK ... LoaD register BANK .................. System Control Instruction...... 121
6.3.18 LDC ........... LoaD to Control register ............. System Control Instruction...... 123
6.3.19 MOV .......... MOVe structure data ................... Data Transfer Instruction......... 124
6.3.20 MOV .......... MOVe reverse stack .................... Data Transfer Instruction......... 127
6.3.21 MOVI20 .... MOVe Immediate 20bits data ..... Data Transfer Instruction......... 130
6.3.22 MOVI20S .. MOVe Immediate 20bits data and 8bits Shift left
...................................................... Data Transfer Instruction......... 131
6.3.23 MOVML.L MOVe Multi-register Lower part Data Transfer Instruction......... 133
6.3.24 MOVMU.L MOVe Multi-register Upper part Data Transfer Instruction......... 136
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6.3.25 MOVRT ..... MOVe Reverse Tbit .................... Data Transfer Instruction......... 139
6.3.26 MOVU ....... MOVe structure data as Unsigned
...................................................... Data Transfer Instruction......... 140
6.3.27 MULR ........ MULtiply to Register .................. Arithmetic Instruction ............. 142
6.3.28 NOTT ........ NOT Tbit ..................................... Data Transfer Instruction......... 143
6.3.29 PREF .......... PREFetch data to cache ............... Data Transfer Instruction......... 144
6.3.30 RESBANK REStore from registerBANK ...... System Control Instruction...... 145
6.3.31 RTS/N ........ ReTurn from Subroutine with No delay slot
...................................................... Branch Instruction ................... 147
6.3.32 RTV/N ....... ReTurn to Value and from subroutine with No delay slot
...................................................... Branch Instruction ................... 148
6.3.33 SHAD ........ SHift Arithmetic Dynamically .... Shift Instruction ....................... 150
6.3.34 SHLD ......... SHift Logical Dynamically ......... Shift Instruction ....................... 152
6.3.35 STBANK ... STore register BANK .................. System Control Instruction...... 154
6.3.36 STC ............ STore Control register ................. System Control Instruction...... 156
6.4 SH-2E CPU Instructions................................................................................................... 157
6.4.1 ADD .......... ADD Binary ................................ Arithmetic Instruction ............. 157
6.4.2 ADDC ........ ADD with Carry .......................... Arithmetic Instruction ............. 158
Rev. 3.00 Jul 08, 2005 page ix of xiv
Datasheet pdf - http://www.DataSheet4U.net/
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