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Numéro de référence | NVD5117PL | ||
Description | Power MOSFET ( Transistor ) | ||
Fabricant | ON Semiconductor | ||
Logo | |||
1 Page
NVD5117PL
Power MOSFET
−60 V, 16 mW, −61 A, Single P−Channel
Features
• Low RDS(on) to Minimize Conduction Losses
• High Current Capability
• Avalanche Energy Specified
• AEC−Q101 Qualified
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain Cur-
rent RqJC (Note 1)
Power Dissipation
(Note 1)
RqJC
Continuous Drain Cur-
rent RqJA (Notes 1 & 2)
Power
(Notes
Dissipation
1 & 2)
RqJA
Pulsed Drain Current
Current Limited by
Package (Note 3)
TC = 25°C
Steady TC = 100°C
State TC = 25°C
TC = 100°C
TA = 25°C
Steady TA = 100°C
State TA = 25°C
TA = 100°C
TA = 25°C, tp = 10 ms
TA = 25°C
VDSS
VGS
ID
PD
ID
PD
IDM
IDmaxpkg
−60
"20
−61
−43
118
59
−11
−8
4.1
2.1
−419
60
V
V
A
W
A
W
A
www.DataSheet.net/
A
Operating Junction and Storage Temperature
TJ, Tstg
−55 to
175
°C
Source Current (Body Diode)
IS −118 A
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL(pk) = 40 A, L = 0.3 mH, RG = 25 W)
EAS 240 mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol Value Unit
Junction−to−Case − Steady State (Drain)
RqJC
1.3 °C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
37
1. The entire application environment impacts the thermal resistance values
shown, they are not constants and are only valid for the particular conditions
noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
http://onsemi.com
V(BR)DSS
−60 V
RDS(on)
16 mW @ −10 V
22 mW @ −4.5 V
S
ID
−61 A
G
P−Channel
D
4
12
3
DPAK
CASE 369C
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENT
4
Drain
2
1 Drain 3
Gate Source
Y
WW
5117L
G
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NVD5117PLT4G DPAK
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
September, 2011 − Rev. 0
1
Publication Order Number:
NVD5117PL/D
Datasheet pdf - http://www.DataSheet4U.co.kr/
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Pages | Pages 6 | ||
Télécharger | [ NVD5117PL ] |
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