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PDF AD9257 Data sheet ( Hoja de datos )
| Número de pieza | AD9257 | |
| Descripción | 1.8V ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9257 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Data Sheet
Octal, 14-Bit, 40/65 MSPS, Serial LVDS,
1.8 V Analog-to-Digital Converter
AD9257
FEATURES
Low power: 55 mW per channel at 65 MSPS with scalable
power options
SNR = 75.5 dB (to Nyquist)
SFDR = 91.6 dBc (to Nyquist)
DNL = ±0.6 LSB (typical), INL = ±1.1 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9257 is an octal, 14-bit, 40 MSPS and 65 MSPS analog-
to-digital converter (ADC) with an on-chip sample-and-hold
circuit designed for low cost, low power, small size, and ease of
use. The product operates at a conversion rate of up to 65 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as programmable clock and data
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
VIN+ A
VIN– A
AD9257
14
ADC
SERIAL
LVDS
D+ A
D– A
VIN+ B
VIN– B
14
ADC
SERIAL
LVDS
D+ B
D– B
VIN+ C
VIN– C
14
ADC
SERIAL
LVDS
D+ C
D– C
VIN+ D
VIN– D
14
ADC
SERIAL
LVDS
D+ D
D– D
VIN+ E
VIN– E
14
ADC
SERIAL
LVDS
D+ E
D– E
VIN+ F
VIN– F
14
ADC
SERIAL
LVDS
D+ F
D– F
VIN+ G
VIN– G
14
ADC
SERIAL
LVDS
D+ G
D– G
VIN+ H
VIN– H
14
ADC
SERIAL
LVDS
D+ H
D– H
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VREF
SENSE
VCM
SYNC
REF
SELECT
1.0V
SERIAL PORT
INTERFACE
DATA
RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
RBIAS
AGND
CSB SDIO/ SCLK/
DFS DTP
Figure 1.
CLK+ CLK–
alignment and programmable digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The AD9257 is available in an RoHS-compliant, 64-lead LFCSP.
It is specified over the industrial temperature range of −40°C
to +85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight ADCs are contained in a small,
space-saving package.
2. Low Power of 55 mW/Channel at 65 MSPS with Scalable
Power Options.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 455 MHz and supports
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
5. Pin Compatible with the AD9637 (12-Bit Octal ADC).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
Data Sheet
AD9257
Parameter1
CROSSTALK
Crosstalk (Overrange Condition)2
ANALOG INPUT BANDWIDTH, FULL POWER
AD9257-40
Temp Min Typ Max
25°C −100
25°C −92
25°C 650
AD9257-65
Min Typ Max
−98
−94
650
Unit
dB
dB
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Overrange condition is specified with 3 dB of the full-scale input range.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D± x), ANSI-644
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D± x), LOW POWER, REDUCED SIGNAL
OPTION
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temp Min
Full 0.2
Full AGND − 0.2
Full
25°C
25°C
Full 1.2
Full 0
25°C
25°C
Full
Full
25°C
25°C
1.2
www.DataSheet.net/
0
Full 1.2
Full 0
25°C
25°C
Full
Full
Full 247
Full 1.13
Full 150
Full 1.13
Typ Max
CMOS/LVDS/LVPECL
3.6
AVDD + 0.2
0.9
15
4
AVDD + 0.2
0.8
30
2
AVDD + 0.2
0.8
26
2
AVDD + 0.2
0.8
26
5
1.79
0.05
LVDS
350 454
1.21 1.38
Twos complement
LVDS
200 250
1.21 1.38
Twos complement
Unit
V p-p
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 This is specified for LVDS and LVPECL only.
3 This is specified for 13 SDIO/DFS pins sharing the same connection.
Rev. 0 | Page 5 of 40
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AD9257-65
0
–15
–30
65MSPS
9.7MHz AT –1dBFS
SNR = 74.7dB (75.7dBFS)
SFDR = 93.5dBc
–45
–60
–75
–90
–105
–120
–135
3 6 9 12 15 18 21 24 27 30
FREQUENCY (MHz)
Figure 6. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 65 MSPS
AD9257
0
65MSPS
–15 19.7MHz AT –1dBFS
SNR = 74.7dB (75.7dBFS)
–30 SFDR = 96.7dBc
–45
–60
–75
–90
–105
–120
–135
3 6 9 12 15 18 21 24 27 30
FREQUENCY (MHz)
Figure 9. Single-Tone 16k FFT with fIN = 19.7 MHz, fSAMPLE = 65 MSPS
0
65MSPS
–15 63.5MHz AT –1dBFS
SNR = 73.9dB (74.9dBFS)
–30 SFDR = 95.4dBc
–45
–60
–75
–90
–105
–120
–135
3 6 9 12 15 18 21 24 27 30
FREQUENCY (MHz)
Figure 7. Single-Tone 16k FFT with fIN = 63.5 MHz, fSAMPLE = 65 MSPS
0
65MSPS
–15 30.5MHz AT –1dBFS
SNR = 74.7dB (75.7dBFS)
–30 SFDR = 96.7dBc
–45
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–60
–75
–90
–105
–120
–135
3 6 9 12 15 18 21 24 27 30
FREQUENCY (MHz)
Figure 10. Single-Tone 16k FFT with fIN = 30.5 MHz, fSAMPLE = 65 MSPS
0
–15
–30
–45
–60
–75
–90
–105
F2 – F1
F1 + F2
2F2 + F1
2F2 – F1
2F1 + F2
2F1 – F2
–120
–135
3 6 9 12 15 18 21 24 27 30
FREQUENCY (MHz)
Figure 8. Two-Tone 16k FFT with fIN1 = 30 MHz and fIN2 = 32 MHz,
fSAMPLE = 65 MSPS
0
65MSPS
–15 123.4MHz AT –1dBFS
SNR = 72.2dB (73.2dBFS)
–30 SFDR = 83.0dBc
–45
–60
–75
–90
–105
–120
–135
3 6 9 12 15 18 21 24 27 30
FREQUENCY (MHz)
Figure 11. Single-Tone 16k FFT with fIN = 123.4 MHz, fSAMPLE = 65 MSPS
Rev. 0 | Page 11 of 40
Datasheet pdf - http://www.DataSheet4U.co.kr/
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