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PDF AD9250 Data sheet ( Hoja de datos )
| Número de pieza | AD9250 | |
| Descripción | Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
14-Bit, 170 MSPS/250 MSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9250
FEATURES
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and
250 MSPS
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz
AIN and 250 MSPS
Total power consumption: 711 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
User-configurable, built-in self-test (BIST) capability
APPLICATIONS
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
I/Q demodulation systems
Smart antenna systems
Electronic test and measurement equipment
Radar receivers
COMSEC radio architectures
IED detection/jamming systems
General-purpose software radios
Broadband data applications
VIN+A
VIN–A
VCM
VIN+B
VIN–B
SYSREF±
SYNCINB±
CLK±
RFCLK
FUNCTIONAL BLOCK DIAGRAM
AVDD DRVDD DVDD
AGND DGND DRGND
AD9250
PIPELINE
14-BIT ADC
PIPELINE
14-BIT ADC
JESD-204B
INTERFACE
HIGH
SPEED
SERIALIZERS
CONTROL
REGISTERS
CML, TX
OUTPUTS
SERDOUT0±
SERDOUT1±
CMOS
DIGITAL
INPUT/
OUTPUT
PDWN
CLOCK
GENERATION
CMOS
DIGITAL
INPUT/OUTPUT
FAST
DETECT
CMOS
DIGITAL
INPUT/
OUTPUT
FDA
FDB
RST
SDIO SCLK CS
Figure 1.
PRODUCT HIGHLIGHTS
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1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
2. The configurable JESD204B output block supports up to
5 Gbps per lane.
3. An on-chip, phase-locked loop (PLL) allows users to provide a
single ADC sampling clock; the PLL multiplies the ADC
sampling clock to produce the corresponding JESD204B
data rate clock.
4. Support for an optional RF clock input to ease system board
design.
5. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
6. Operation from a single 1.8 V power supply.
7. Standard serial port interface (SPI) that supports various
product features and functions such as controlling the clock
DCS, power-down, test modes, voltage reference mode, over
range fast detection, and serial output configuration.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
Data Sheet
AD9250
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
Temperature
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
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25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
AD9250-170
AD9250-250
Min Typ Max Min Typ Max Unit
72.5
72.0
70.7
71.4
70.7
70.1
72.1
71.7
71.2
70.6
69.3
70.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
71.3
70.9
69.6
70.3
69.6
68.9
70.7
70.5
70.0
69.5
68.0
68.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
11.5 11.5 Bits
11.4 11.4 Bits
11.3 11.3 Bits
11.1 11.2 Bits
10.9 11.0 Bits
92
95
78
91
86
85
89
86
86
88
80
88
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−92
−95
−78
−91
−86
−85
−89 dBc
−87 dBc
dBc
−86 dBc
−88 dBc
−80 dBc
−88 dBc
−95
−94
−78
−97
−96
−93
−94 dBc
−96 dBc
dBc
−96 dBc
−88 dBc
−80 dBc
−91 dBc
Rev. 0 | Page 5 of 44
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9250
AVDD 1
RFCLK 2
CLK– 3
CLK+ 4
AVDD 5
SYSREF+ 6
SYSREF– 7
AVDD 8
DVDD 9
RST 10
DVDD 11
DNC 12
AD9250
TOP VIEW
(Not to Scale)
36 AVDD
35 DNC
34 PDWN
33 CS
32 SCLK
31 SDIO
30 DVDD
29 DNC
28 DNC
27 FDA
26 FDB
25 DVDD
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE
PACKAGE PROVIDES THE GROUND REFERENCE FOR
DRVDD AND AVDD. THIS EXPOSED PADDLE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 4. Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
ADC Power Supplies
1, 5, 8, 36, 37, 40, 41, 43, 44, 47, 48
9, 11, 13, 16, 24, 25, 30
12, 28, 29, 35
17, 23
20
Mnemonic
AVDD
DVDD
DNC
DGND
DRVDD
Exposed Paddle
AGND/DRGND
ADC Analog
2
3
4
38
39
42
45
46
ADC Fast Detect Outputs
26
27
Digital Inputs
6
7
14
15
RFCLK
CLK−
CLK+
VIN−A
VIN+A
VCM
VIN+B
VIN−B
FDB
FDA
SYSREF+
SYSREF−
SYNCINB+
SYNCINB−
Type
Description
Supply
Supply
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Supply
Ground
Analog Power Supply (1.8 V Nominal).
Digital Power Supply (1.8 V Nominal).
Do Not Connect.
Ground Reference for DVDD.
JESD204B PHY Serial Output Driver Supply (1.8 V Nominal).
Note that the DRVDD power is referenced to the AGND Plane.
The exposed thermal paddle on the bottom of the package
provides the ground reference for DRVDD and AVDD. This
exposed paddle must be connected to ground for proper
operation.
Input
Input
Input
Input
Input
Output
Input
Input
ADC RF Clock Input.
ADC Nyquist Clock Input—Complement.
ADC Nyquist Clock Input—True.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel A.
Common-Mode Level Bias Output for Analog Inputs. Decouple
this pin to ground using a 0.1 µF capacitor.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Output
Output
Channel B Fast Detect Indicator (CMOS Levels).
Channel A Fast Detect Indicator (CMOS Levels).
Input
Input
Input
Input
Active Low JESD204B LVDS SYSREF Input—True
Active Low JESD204B LVDS SYSREF Input—Complement.
Active Low JESD204B LVDS SYNC Input—True
Active Low JESD204B LVDS SYNC Input—Complement.
Rev. 0 | Page 11 of 44
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9250.PDF ] | |
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