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BU-61570 fiches techniques PDF

DDC - (BU-61580 - BU-61585) MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT

Numéro de référence BU-61570
Description (BU-61580 - BU-61585) MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT
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BU-61570 fiche technique
BU-65170/61580 and BU-61585
MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT,
ADVANCED COMMUNICATION ENGINE (ACE)
ACE User’s Guide
Also Available
DESCRIPTION
DDC's BU-65170, BU-61580 and
BU-61585 Bus Controller / Remote
Terminal / Monitor Terminal
(BC/RT/MT)
Advanced
Communication Engine (ACE) termi-
nals comprise a complete integrated
interface between a host processor
and a MIL-STD-1553 A and B or
STANAG 3838 bus.
configured as 12K x 16 or 8K x 17.
The 8K x 17 RAM feature provides
capability for memory integrity check-
ing by implementing RAM parity gen-
eration and verification on all access-
es. To minimize board space and
“glue” logic, the ACE provides ultimate
flexibility in interfacing to a host
processor and internal/external RAM.
The ACE series is packaged in a 1.9 -
square-inch, 70-pin, low-profile,
cofired MultiChip Module (MCM)
ceramic package that is well suited for
applications with stringent height
requirements.
The BU-61585 ACE integrates dual
transceiver, protocol, memory man-
agement, processor interface logic,
and a total of 12K words of RAM in a
choice of DIP or flat pack packages.
The BU-61585 requires +5 V power
and either -15 V or -12 V power.
The BU-61585 internal RAM can be
The advanced functional architecture
of the ACE terminals provides soft-
ware compatibility to DDC's
Advanced Integrated Multiplexer (AIM)
series hybrids, while incorporating a
multiplicity of architectural enhance-
ments. It allows flexible operation
while off-loading the host processor,
ensuring data sample consistency,
and supports bulk data transfers.
The ACE hybrids may be operated at
either 12 or 16 MHz. Wire bond
options allow for programmable RThttp://www.DataSheet4U.net/
address (hardwired is standard) and
external transmitter inhibit inputs.
FEATURES
Fully Integrated MIL-STD-1553
Interface Terminal
Flexible Processor/Memory
Interface
Standard 4K x 16 RAM and
Optional 12K x 16 or 8K x 17 RAM
Available
Optional RAM Parity
Generation/Checking
Automatic BC Retries
Programmable BC Gap Times
BC Frame Auto-Repeat
Flexible RT Data Buffering
Programmable Illegalization
Selective Message Monitor
Simultaneous RT/Monitor Mode
CH. A
TX/RX_A
TRANSCEIVER
A
TX/RX_A
TX/RX_B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
*SHARED
RAM
DATA BUS
ADDRESS BUS
DATA
BUFFERS
ADDRESS
BUFFERS
D15-D0
A15-A0
PROCESSOR
DATA BUS
PROCESSOR
ADDRESS BUS
CH. B
TRANSCEIVER
B
RT ADDRESS
MISCELLANEOUS
TX/RX_B
RTAD4-RTAD0, RTADP
INCMD
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
PROCESSOR
AND
MEMORY
CONTROL
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
INT INTERRUPT
REQUEST
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
FIGURE 1. ACE BLOCK DIAGRAM
© 1992, 1999 Data Device Corporation
datasheet pdf - http://www.DataSheet4U.net/

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