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PDF UM10204 Data sheet ( Hoja de datos )
| Número de pieza | UM10204 | |
| Descripción | I2C-bus specification and user manual | |
| Fabricantes | NXP Semiconductors | |
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UM10204
I2C-bus specification and user manual
Rev. 4 — 13 February 2012
User manual
Document information
Info Content
Keywords
I2C, I2C-bus, Standard-mode, Fast-mode, Fast-mode Plus, Fm+,
Ultra Fast-mode, UFm, High Speed, Hs, inter-IC, SDA, SCL, USDA, USCL
Abstract
Philips Semiconductors (now NXP Semiconductors) developed a simple
bidirectional 2-wire bus for efficient inter-IC control. This bus is called the
Inter-IC or I2C-bus. Only two bus lines are required: a serial data line
(SDA) and a serial clock line (SCL). Serial, 8-bit oriented, bidirectional
data transfers can be made at up to 100 kbit/s in the Standard-mode, up to
400 kbit/s in the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus (Fm+), or
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up to 3.4 Mbit/s in the High-speed mode. The Ultra Fast-mode is a
uni-directional mode with data transfers of up to 5 Mbit/s.
datasheet pdf - http://www.DataSheet4U.net/
1 page  
NXP Semiconductors
UM10204
I2C-bus specification and user manual
• Integrated addressing and data-transfer protocol allow systems to be completely
software-defined.
• The same IC types can often be used in many different applications.
• Design-time reduces as designers quickly become familiar with the frequently used
functional blocks represented by I2C-bus compatible ICs.
• ICs can be added to or removed from a system without affecting any other circuits on
the bus.
• Fault diagnosis and debugging are simple; malfunctions can be immediately traced.
• Software development time can be reduced by assembling a library of reusable
software modules.
In addition to these advantages, the CMOS ICs in the I2C-bus compatible range offer
designers special features which are particularly attractive for portable equipment and
battery-backed systems.
They all have:
• Extremely low current consumption
• High noise immunity
• Wide supply voltage range
• Wide operating temperature range.
2.2 Manufacturer benefits
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I2C-bus compatible ICs not only assist designers, they also give a wide range of benefits
to equipment manufacturers because:
• The simple 2-wire serial I2C-bus minimizes interconnections so ICs have fewer pins
and there are not so many PCB tracks; result — smaller and less expensive PCBs.
• The completely integrated I2C-bus protocol eliminates the need for address decoders
and other ‘glue logic’.
• The multi-master capability of the I2C-bus allows rapid testing and alignment of
end-user equipment via external connections to an assembly line.
• The availability of I2C-bus compatible ICs in various leadless packages reduces
space requirements even more.
These are just some of the benefits. In addition, I2C-bus compatible ICs increase system
design flexibility by allowing simple construction of equipment variants and easy
upgrading to keep designs up-to-date. In this way, an entire family of equipment can be
developed around a basic model. Upgrades for new equipment, or enhanced-feature
models (that is, extended memory, remote control, etc.) can then be produced simply by
clipping the appropriate ICs onto the bus. If a larger ROM is needed, it is simply a matter
of selecting a microcontroller with a larger ROM from our comprehensive range. As new
ICs supersede older ones, it is easy to add new features to equipment or to increase its
performance by simply unclipping the outdated IC from the bus and clipping on its
successor.
UM10204
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 13 February 2012
© NXP B.V. 2012. All rights reserved.
5 of 64
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NXP Semiconductors
UM10204
I2C-bus specification and user manual
3.1.7 Clock synchronization
Two masters can begin transmitting on an idle bus at the same time and there must be a
method for deciding which takes control of the bus and complete its transmission. This is
done by clock synchronization and arbitration. In single master systems, clock
synchronization and arbitration are not needed.
Clock synchronization is performed using the wired-AND connection of I2C interfaces to
the SCL line. This means that a HIGH to LOW transition on the SCL line causes the
masters concerned to start counting off their LOW period and, once a master clock has
gone LOW, it holds the SCL line in that state until the clock HIGH state is reached (see
Figure 7). However, if another clock is still within its LOW period, the LOW to HIGH
transition of this clock may not change the state of the SCL line. The SCL line is therefore
held LOW by the master with the longest LOW period. Masters with shorter LOW periods
enter a HIGH wait-state during this time.
CLK
1
wait
state
start counting
HIGH period
counter
CLK
reset
2
SCL
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mbc632
Fig 7. Clock synchronization during the arbitration procedure
When all masters concerned have counted off their LOW period, the clock line is released
and goes HIGH. There is then no difference between the master clocks and the state of
the SCL line, and all the masters start counting their HIGH periods. The first master to
complete its HIGH period pulls the SCL line LOW again.
In this way, a synchronized SCL clock is generated with its LOW period determined by the
master with the longest clock LOW period, and its HIGH period determined by the one
with the shortest clock HIGH period.
3.1.8 Arbitration
Arbitration, like synchronization, refers to a portion of the protocol required only if more
than one master is used in the system. Slaves are not involved in the arbitration
procedure. A master may start a transfer only if the bus is free. Two masters may
generate a START condition within the minimum hold time (tHD;STA) of the START
condition which results in a valid START condition on the bus. Arbitration is then required
to determine which master will complete its transmission.
Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each master checks to
see if the SDA level matches what it has sent. This process may take many bits. Two
masters can actually complete an entire transaction without error, as long as the
UM10204
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 13 February 2012
© NXP B.V. 2012. All rights reserved.
11 of 64
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